From 34a0fad10210a3e639a8e68323c923494047eefc Mon Sep 17 00:00:00 2001 From: Tom Musta Date: Tue, 12 Aug 2014 08:45:09 -0500 Subject: target-ppc: Bug Fix: srawi For 64 bit implementations, the special case of a shift by zero should result in the sign extension of the least significant 32 bits of the source GPR (not a direct copy of the 64 bit source GPR). Example: R3 A6212433228F41DC srawi 3,3,0 R3 expected : 00000000228F41DC R3 actual : A6212433228F41DC (without this patch) Signed-off-by: Tom Musta Signed-off-by: Alexander Graf --- target-ppc/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'target-ppc') diff --git a/target-ppc/translate.c b/target-ppc/translate.c index b19eb14df7..47dc90311c 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -1944,7 +1944,7 @@ static void gen_srawi(DisasContext *ctx) TCGv dst = cpu_gpr[rA(ctx->opcode)]; TCGv src = cpu_gpr[rS(ctx->opcode)]; if (sh == 0) { - tcg_gen_mov_tl(dst, src); + tcg_gen_ext32s_tl(dst, src); tcg_gen_movi_tl(cpu_ca, 0); } else { TCGv t0; -- cgit v1.2.1