From 16c358e96e0597b7d60754547166ad05ecc6d93d Mon Sep 17 00:00:00 2001 From: Sebastian Huber Date: Tue, 11 Mar 2014 10:36:00 +0100 Subject: target-sparc: Add and use CPU_FEATURE_CASA MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The LEON3 processor has support for the CASA instruction which is normally only available for SPARC V9 processors. Binutils 2.24 and GCC 4.9 will support this instruction for LEON3. GCC uses it to generate C11 atomic operations. The CAS synthetic instruction uses an ASI of 0x80. If TARGET_SPARC64 is not defined use a supervisor data load/store for an ASI of 0x80 in helper_ld_asi()/helper_st_asi(). The supervisor data load/store was choosen according to the LEON3 documentation. The ASI 0x80 is defined in the SPARC V9 manual, Table 12—Address Space Identifiers (ASIs). Here we have: 0x80, ASI_PRIMARY, Unrestricted access, Primary address space. Tested with the following program: #include #include void test(void) { atomic_int a; int e; _Bool b; atomic_store(&a, 1); e = 1; b = atomic_compare_exchange_strong(&a, &e, 2); assert(b); assert(atomic_load(&a) == 2); atomic_store(&a, 3); e = 4; b = atomic_compare_exchange_strong(&a, &e, 5); assert(!b); assert(atomic_load(&a) == 3); } Tested also on a NGMP board with a LEON4 processor. Reviewed-by: Fabien Chouteau Reviewed-by: Andreas Färber Tested-by: Mark Cave-Ayland Reviewed-by: Richard Henderson Signed-off-by: Sebastian Huber Signed-off-by: Mark Cave-Ayland --- target-sparc/ldst_helper.c | 28 ++++++++++++++++------------ 1 file changed, 16 insertions(+), 12 deletions(-) (limited to 'target-sparc/ldst_helper.c') diff --git a/target-sparc/ldst_helper.c b/target-sparc/ldst_helper.c index 92761ad17b..32491b499a 100644 --- a/target-sparc/ldst_helper.c +++ b/target-sparc/ldst_helper.c @@ -584,6 +584,7 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size, } break; case 0xb: /* Supervisor data access */ + case 0x80: switch (size) { case 1: ret = cpu_ldub_kernel(env, addr); @@ -955,6 +956,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, int asi, } break; case 0xb: /* Supervisor data access */ + case 0x80: switch (size) { case 1: cpu_stb_kernel(env, addr, val); @@ -2232,33 +2234,35 @@ void helper_stf_asi(CPUSPARCState *env, target_ulong addr, int asi, int size, } } -target_ulong helper_cas_asi(CPUSPARCState *env, target_ulong addr, - target_ulong val1, target_ulong val2, uint32_t asi) +target_ulong helper_casx_asi(CPUSPARCState *env, target_ulong addr, + target_ulong val1, target_ulong val2, + uint32_t asi) { target_ulong ret; - val2 &= 0xffffffffUL; - ret = helper_ld_asi(env, addr, asi, 4, 0); - ret &= 0xffffffffUL; + ret = helper_ld_asi(env, addr, asi, 8, 0); if (val2 == ret) { - helper_st_asi(env, addr, val1 & 0xffffffffUL, asi, 4); + helper_st_asi(env, addr, val1, asi, 8); } return ret; } +#endif /* TARGET_SPARC64 */ -target_ulong helper_casx_asi(CPUSPARCState *env, target_ulong addr, - target_ulong val1, target_ulong val2, - uint32_t asi) +#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) +target_ulong helper_cas_asi(CPUSPARCState *env, target_ulong addr, + target_ulong val1, target_ulong val2, uint32_t asi) { target_ulong ret; - ret = helper_ld_asi(env, addr, asi, 8, 0); + val2 &= 0xffffffffUL; + ret = helper_ld_asi(env, addr, asi, 4, 0); + ret &= 0xffffffffUL; if (val2 == ret) { - helper_st_asi(env, addr, val1, asi, 8); + helper_st_asi(env, addr, val1 & 0xffffffffUL, asi, 4); } return ret; } -#endif /* TARGET_SPARC64 */ +#endif /* !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) */ void helper_ldqf(CPUSPARCState *env, target_ulong addr, int mem_idx) { -- cgit v1.2.1