From 664a65b0dbd9a4845ac7d3c21e8b103031ee57f2 Mon Sep 17 00:00:00 2001 From: "Igor V. Kovalenko" Date: Sat, 22 May 2010 14:52:40 +0400 Subject: sparc64: flush translations on mmu context change - two pairs of softmmu indexes bind softmmu tlb to cpu tlb in fault handlers using value of DMMU primary and secondary context registers, so we need to flush softmmu translations when context registers are changed Signed-off-by: Igor V. Kovalenko Signed-off-by: Blue Swirl --- target-sparc/op_helper.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'target-sparc/op_helper.c') diff --git a/target-sparc/op_helper.c b/target-sparc/op_helper.c index 28224b23dc..edeeb4469a 100644 --- a/target-sparc/op_helper.c +++ b/target-sparc/op_helper.c @@ -2959,9 +2959,15 @@ void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size) break; case 1: // Primary context env->dmmu.mmu_primary_context = val; + /* can be optimized to only flush MMU_USER_IDX + and MMU_KERNEL_IDX entries */ + tlb_flush(env, 1); break; case 2: // Secondary context env->dmmu.mmu_secondary_context = val; + /* can be optimized to only flush MMU_USER_SECONDARY_IDX + and MMU_KERNEL_SECONDARY_IDX entries */ + tlb_flush(env, 1); break; case 5: // TSB access DPRINTF_MMU("dmmu TSB write: 0x%016" PRIx64 " -> 0x%016" -- cgit v1.2.1