From a0e372f0c49ac01faeaeb73a6e8f50e8ac615f34 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Fri, 28 Jun 2013 23:18:47 +0200 Subject: cpu: Introduce CPUState::gdb_num_regs and CPUClass::gdb_num_core_regs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit CPUState::gdb_num_regs replaces num_g_regs. CPUClass::gdb_num_core_regs replaces NUM_CORE_REGS. Allows building gdb_register_coprocessor() for xtensa, too. As a side effect this should fix coprocessor register numbering for SMP. Acked-by: Michael Walle (for lm32) Acked-by: Max Filippov (for xtensa) Signed-off-by: Andreas Färber --- target-xtensa/cpu.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'target-xtensa/cpu.c') diff --git a/target-xtensa/cpu.c b/target-xtensa/cpu.c index 5a39971d2c..560fa0c058 100644 --- a/target-xtensa/cpu.c +++ b/target-xtensa/cpu.c @@ -85,8 +85,11 @@ static ObjectClass *xtensa_cpu_class_by_name(const char *cpu_model) static void xtensa_cpu_realizefn(DeviceState *dev, Error **errp) { + CPUState *cs = CPU(dev); XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(dev); + cs->gdb_num_regs = xcc->config->gdb_regmap.num_regs; + xcc->parent_realize(dev, errp); } -- cgit v1.2.1