From dd519cbec63434f2b883f0b4a20f827bbd59793e Mon Sep 17 00:00:00 2001 From: Max Filippov Date: Wed, 19 Sep 2012 04:23:54 +0400 Subject: target-xtensa: add FP registers There are 16 32-bit FP registers (f0 - f15), control and status user registers (fcr, fsr). See ISA, 4.3.10 for more details. Signed-off-by: Max Filippov Signed-off-by: Blue Swirl --- target-xtensa/cpu.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'target-xtensa/cpu.h') diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h index 177094ae9a..b4562832b3 100644 --- a/target-xtensa/cpu.h +++ b/target-xtensa/cpu.h @@ -36,6 +36,7 @@ #include "config.h" #include "qemu-common.h" #include "cpu-defs.h" +#include "fpu/softfloat.h" #define TARGET_HAS_ICE 1 @@ -325,6 +326,8 @@ typedef struct CPUXtensaState { uint32_t sregs[256]; uint32_t uregs[256]; uint32_t phys_regs[MAX_NAREG]; + float32 fregs[16]; + float_status fp_status; xtensa_tlb_entry itlb[7][MAX_TLB_WAY_SIZE]; xtensa_tlb_entry dtlb[10][MAX_TLB_WAY_SIZE]; -- cgit v1.2.1