From 5739006b9ab1ae3680359db5a291eae97eef0f9f Mon Sep 17 00:00:00 2001 From: Max Filippov Date: Mon, 21 Jan 2013 18:40:04 +0400 Subject: target-xtensa: add fallthrough markers Explicitly mark cases where we are deliberately falling through to the following code. Signed-off-by: Max Filippov --- target-xtensa/op_helper.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'target-xtensa') diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c index 4c41de0668..834fe9087d 100644 --- a/target-xtensa/op_helper.c +++ b/target-xtensa/op_helper.c @@ -448,8 +448,10 @@ void HELPER(check_atomctl)(CPUXtensaState *env, uint32_t pc, uint32_t vaddr) switch (access & PAGE_CACHE_MASK) { case PAGE_CACHE_WB: atomctl >>= 2; + /* fall through */ case PAGE_CACHE_WT: atomctl >>= 2; + /* fall through */ case PAGE_CACHE_BYPASS: if ((atomctl & 0x3) == 0) { HELPER(exception_cause_vaddr)(env, pc, -- cgit v1.2.1 From a00817cc4c18b7872e92765a4736fb2227cc237b Mon Sep 17 00:00:00 2001 From: Max Filippov Date: Mon, 4 Mar 2013 07:02:00 +0400 Subject: target-xtensa: avoid double-stopping at breakpoints env->exception_taken is set every time an exception is taken. It is used to allow single-stepping to stop at the first exception handler instruction. This however must exclude debug exceptions, as otherwise first step from the instruction where breakpoint was hit stops at that same instruction. Also don't check env->exception_taken directly from the gen_intermediate_code_internal, instead allocate and use TB flag XTENSA_TBFLAG_EXCEPTION. Signed-off-by: Max Filippov --- target-xtensa/cpu.h | 4 ++++ target-xtensa/op_helper.c | 3 +++ target-xtensa/translate.c | 3 +-- 3 files changed, 8 insertions(+), 2 deletions(-) (limited to 'target-xtensa') diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h index a8f02f6e4b..95103e9e87 100644 --- a/target-xtensa/cpu.h +++ b/target-xtensa/cpu.h @@ -484,6 +484,7 @@ static inline int cpu_mmu_index(CPUXtensaState *env) #define XTENSA_TBFLAG_ICOUNT 0x20 #define XTENSA_TBFLAG_CPENABLE_MASK 0x3fc0 #define XTENSA_TBFLAG_CPENABLE_SHIFT 6 +#define XTENSA_TBFLAG_EXCEPTION 0x4000 static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong *pc, target_ulong *cs_base, int *flags) @@ -510,6 +511,9 @@ static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong *pc, if (xtensa_option_enabled(env->config, XTENSA_OPTION_COPROCESSOR)) { *flags |= env->sregs[CPENABLE] << XTENSA_TBFLAG_CPENABLE_SHIFT; } + if (ENV_GET_CPU(env)->singlestep_enabled && env->exception_taken) { + *flags |= XTENSA_TBFLAG_EXCEPTION; + } } #include "exec/cpu-all.h" diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c index 834fe9087d..6ca912c5bb 100644 --- a/target-xtensa/op_helper.c +++ b/target-xtensa/op_helper.c @@ -96,6 +96,9 @@ static void tb_invalidate_virtual_addr(CPUXtensaState *env, uint32_t vaddr) void HELPER(exception)(CPUXtensaState *env, uint32_t excp) { env->exception_index = excp; + if (excp == EXCP_DEBUG) { + env->exception_taken = 0; + } cpu_loop_exit(env); } diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c index e692329157..7ea5e2ae16 100644 --- a/target-xtensa/translate.c +++ b/target-xtensa/translate.c @@ -2918,8 +2918,7 @@ void gen_intermediate_code_internal(XtensaCPU *cpu, gen_tb_start(); - if (cs->singlestep_enabled && env->exception_taken) { - env->exception_taken = 0; + if (tb->flags & XTENSA_TBFLAG_EXCEPTION) { tcg_gen_movi_i32(cpu_pc, dc.pc); gen_exception(&dc, EXCP_DEBUG); } -- cgit v1.2.1 From 0857a06ef784783887e756d4b7b5f874512c506c Mon Sep 17 00:00:00 2001 From: Max Filippov Date: Sun, 21 Jul 2013 07:54:37 +0400 Subject: target-xtensa: don't generate dead code to access invalid SRs This fixes the following test failure caused by access to undefined SR: qemu-system-xtensa -M sim -cpu dc232b -nographic -semihosting -kernel ./test_sr.tst QEMU 1.4.50 monitor - type 'help' for more information (qemu) QEMU 1.4.50 monitor - type 'help' for more information (qemu) qemu-system-xtensa: tcg/tcg.c:1673: temp_save: Assertion `s->temps[temp].val_type == 2 || s->temps[temp].fixed_reg' failed. Signed-off-by: Max Filippov --- target-xtensa/translate.c | 31 ++++++++++++++++++------------- 1 file changed, 18 insertions(+), 13 deletions(-) (limited to 'target-xtensa') diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c index 7ea5e2ae16..15fab1ba30 100644 --- a/target-xtensa/translate.c +++ b/target-xtensa/translate.c @@ -491,7 +491,7 @@ static void gen_brcondi(DisasContext *dc, TCGCond cond, tcg_temp_free(tmp); } -static void gen_check_sr(DisasContext *dc, uint32_t sr, unsigned access) +static bool gen_check_sr(DisasContext *dc, uint32_t sr, unsigned access) { if (!xtensa_option_bits_enabled(dc->config, sregnames[sr].opt_bits)) { if (sregnames[sr].name) { @@ -500,6 +500,7 @@ static void gen_check_sr(DisasContext *dc, uint32_t sr, unsigned access) qemu_log("SR %d is not implemented\n", sr); } gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE); + return false; } else if (!(sregnames[sr].access & access)) { static const char * const access_text[] = { [SR_R] = "rsr", @@ -510,7 +511,9 @@ static void gen_check_sr(DisasContext *dc, uint32_t sr, unsigned access) qemu_log("SR %s is not available for %s\n", sregnames[sr].name, access_text[access]); gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE); + return false; } + return true; } static void gen_rsr_ccount(DisasContext *dc, TCGv_i32 d, uint32_t sr) @@ -1482,9 +1485,9 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc) break; case 6: /*XSR*/ - { + if (gen_check_sr(dc, RSR_SR, SR_X)) { TCGv_i32 tmp = tcg_temp_new_i32(); - gen_check_sr(dc, RSR_SR, SR_X); + if (RSR_SR >= 64) { gen_check_privilege(dc); } @@ -1707,21 +1710,23 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc) case 3: /*RST3*/ switch (OP2) { case 0: /*RSR*/ - gen_check_sr(dc, RSR_SR, SR_R); - if (RSR_SR >= 64) { - gen_check_privilege(dc); + if (gen_check_sr(dc, RSR_SR, SR_R)) { + if (RSR_SR >= 64) { + gen_check_privilege(dc); + } + gen_window_check1(dc, RRR_T); + gen_rsr(dc, cpu_R[RRR_T], RSR_SR); } - gen_window_check1(dc, RRR_T); - gen_rsr(dc, cpu_R[RRR_T], RSR_SR); break; case 1: /*WSR*/ - gen_check_sr(dc, RSR_SR, SR_W); - if (RSR_SR >= 64) { - gen_check_privilege(dc); + if (gen_check_sr(dc, RSR_SR, SR_W)) { + if (RSR_SR >= 64) { + gen_check_privilege(dc); + } + gen_window_check1(dc, RRR_T); + gen_wsr(dc, RSR_SR, cpu_R[RRR_T]); } - gen_window_check1(dc, RRR_T); - gen_wsr(dc, RSR_SR, cpu_R[RRR_T]); break; case 2: /*SEXTu*/ -- cgit v1.2.1 From 908c67fca4b2c12a9b2336aa9c188f84468b60b7 Mon Sep 17 00:00:00 2001 From: Max Filippov Date: Sun, 21 Jul 2013 12:55:46 +0400 Subject: target-xtensa: check register window inline This lowers time spent in helper_window_check as reported by perf top from ~8% to ~0.15% accelerating register-intensive tests by ~20%. Signed-off-by: Max Filippov --- target-xtensa/translate.c | 33 +++++++++++++++++++++++++-------- 1 file changed, 25 insertions(+), 8 deletions(-) (limited to 'target-xtensa') diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c index 15fab1ba30..504cc539e3 100644 --- a/target-xtensa/translate.c +++ b/target-xtensa/translate.c @@ -305,16 +305,21 @@ static void gen_left_shift_sar(DisasContext *dc, TCGv_i32 sa) tcg_temp_free(tmp); } -static void gen_advance_ccount(DisasContext *dc) +static void gen_advance_ccount_cond(DisasContext *dc) { if (dc->ccount_delta > 0) { TCGv_i32 tmp = tcg_const_i32(dc->ccount_delta); - dc->ccount_delta = 0; gen_helper_advance_ccount(cpu_env, tmp); tcg_temp_free(tmp); } } +static void gen_advance_ccount(DisasContext *dc) +{ + gen_advance_ccount_cond(dc); + dc->ccount_delta = 0; +} + static void reset_used_window(DisasContext *dc) { dc->used_window = 0; @@ -829,15 +834,27 @@ static void gen_window_check1(DisasContext *dc, unsigned r1) } if (option_enabled(dc, XTENSA_OPTION_WINDOWED_REGISTER) && r1 / 4 > dc->used_window) { - TCGv_i32 pc = tcg_const_i32(dc->pc); - TCGv_i32 w = tcg_const_i32(r1 / 4); + int label = gen_new_label(); + TCGv_i32 ws = tcg_temp_new_i32(); dc->used_window = r1 / 4; - gen_advance_ccount(dc); - gen_helper_window_check(cpu_env, pc, w); + tcg_gen_deposit_i32(ws, cpu_SR[WINDOW_START], cpu_SR[WINDOW_START], + dc->config->nareg / 4, dc->config->nareg / 4); + tcg_gen_shr_i32(ws, ws, cpu_SR[WINDOW_BASE]); + tcg_gen_andi_i32(ws, ws, (2 << (r1 / 4)) - 2); + tcg_gen_brcondi_i32(TCG_COND_EQ, ws, 0, label); + { + TCGv_i32 pc = tcg_const_i32(dc->pc); + TCGv_i32 w = tcg_const_i32(r1 / 4); + + gen_advance_ccount_cond(dc); + gen_helper_window_check(cpu_env, pc, w); - tcg_temp_free(w); - tcg_temp_free(pc); + tcg_temp_free(w); + tcg_temp_free(pc); + } + gen_set_label(label); + tcg_temp_free(ws); } } -- cgit v1.2.1