From 89854803ce3efb16fbc94604e652f152f5102569 Mon Sep 17 00:00:00 2001 From: Michael Clark Date: Mon, 5 Mar 2018 20:22:30 +1300 Subject: RISC-V: Remove EM_RISCV ELF_MACHINE indirection MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Pointless indirection. Other ports use EM_ constants directly. Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 1 - 1 file changed, 1 deletion(-) (limited to 'target/riscv/cpu.h') diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 41e06ac0f9..9871e6feb1 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -34,7 +34,6 @@ #define TCG_GUEST_DEFAULT_MO 0 -#define ELF_MACHINE EM_RISCV #define CPUArchState struct CPURISCVState #include "qemu-common.h" -- cgit v1.2.1 From 79f86934267135080e13e02b52c74371220d8e06 Mon Sep 17 00:00:00 2001 From: Michael Clark Date: Mon, 5 Mar 2018 13:28:00 +1300 Subject: RISC-V: Update E and I extension order Section 22.8 Subset Naming Convention of the RISC-V ISA Specification defines the canonical order for extensions in the ISA string. It is silent on the position of the E extension however E is a substitute for I so it must come early in the extension list order. A comment is added to state E and I are mutually exclusive, as the E extension will be added to the RISC-V port in the future. Cc: Sagar Karandikar Cc: Bastian Koppelmann Cc: Palmer Dabbelt Cc: Alistair Francis Signed-off-by: Michael Clark Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 1 + 1 file changed, 1 insertion(+) (limited to 'target/riscv/cpu.h') diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 9871e6feb1..1dcbdbe6f7 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -71,6 +71,7 @@ #define RV(x) ((target_ulong)1 << (x - 'A')) #define RVI RV('I') +#define RVE RV('E') /* E and I are mutually exclusive */ #define RVM RV('M') #define RVA RV('A') #define RVF RV('F') -- cgit v1.2.1 From 8c59f5c1b5aabbad92871bf62bb302fef017e322 Mon Sep 17 00:00:00 2001 From: Michael Clark Date: Mon, 9 Apr 2018 11:33:05 +1200 Subject: RISC-V: Use [ms]counteren CSRs when priv ISA >= v1.10 Privileged ISA v1.9.1 defines mscounteren and mucounteren: * mscounteren contains a mask of counters available to S-mode * mucounteren contains a mask of counters available to U-mode Privileged ISA v1.10 defines mcounteren and scounteren: * mcounteren contains a mask of counters available to S-mode * scounteren contains a mask of counters available to U-mode mcounteren and scounteren CSR registers were implemented however they were not honoured for counter accesses when the privilege ISA was >= v1.10. This fix solves the issue by coalescing the counter enable registers. In addition the code now generates illegal instruction exceptions for accesses to the counter enabled registers depending on the privileged ISA version. - Coalesce mscounteren and mcounteren into one variable - Coalesce mucounteren and scounteren into one variable - Makes mcounteren and scounteren CSR accesses generate illegal instructions when the privileged ISA <= v1.9.1 - Makes mscounteren and mucounteren CSR accesses generate illegal instructions when the privileged ISA >= v1.10 Cc: Sagar Karandikar Cc: Bastian Koppelmann Cc: Palmer Dabbelt Cc: Alistair Francis Signed-off-by: Michael Clark --- target/riscv/cpu.h | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'target/riscv/cpu.h') diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 1dcbdbe6f7..34abc383e3 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -151,10 +151,8 @@ struct CPURISCVState { target_ulong mcause; target_ulong mtval; /* since: priv-1.10.0 */ - uint32_t mucounteren; - uint32_t mscounteren; - target_ulong scounteren; /* since: priv-1.10.0 */ - target_ulong mcounteren; /* since: priv-1.10.0 */ + target_ulong scounteren; + target_ulong mcounteren; target_ulong sscratch; target_ulong mscratch; -- cgit v1.2.1