From e72c4fb81db52be881c9356f1c60e0a7817d2d32 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Thu, 30 Jul 2015 23:39:34 +0200 Subject: tcg/mips: fix TLB loading for BE host with 32-bit guests For 32-bit guest, we load a 32-bit address from the TLB, so there is no need to compensate for the low or high part. This fixes 32-bit guests on big-endian hosts. Cc: qemu-stable@nongnu.org Reviewed-by: Richard Henderson Signed-off-by: Aurelien Jarno --- tcg/mips/tcg-target.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'tcg') diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c index 668029977c..8dce19cdba 100644 --- a/tcg/mips/tcg-target.c +++ b/tcg/mips/tcg-target.c @@ -963,9 +963,11 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg base, TCGReg addrl, } /* Load the tlb comparator. */ - tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, TCG_REG_A0, cmp_off + LO_OFF); if (TARGET_LONG_BITS == 64) { + tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, TCG_REG_A0, cmp_off + LO_OFF); tcg_out_opc_imm(s, OPC_LW, base, TCG_REG_A0, cmp_off + HI_OFF); + } else { + tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, TCG_REG_A0, cmp_off); } /* Mask the page bits, keeping the alignment bits to compare against. -- cgit v1.2.1