From e24dc9feb0d68142d54dc3c097f57588836d1338 Mon Sep 17 00:00:00 2001 From: Stefan Weil Date: Tue, 18 Sep 2012 22:52:14 +0200 Subject: tci: Support deposit operations The operations for INDEX_op_deposit_i32 and INDEX_op_deposit_i64 are now supported and enabled by default. Signed-off-by: Stefan Weil Signed-off-by: Blue Swirl --- tci.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'tci.c') diff --git a/tci.c b/tci.c index 98f5f713e0..9c87c8e8b3 100644 --- a/tci.c +++ b/tci.c @@ -688,6 +688,17 @@ tcg_target_ulong tcg_qemu_tb_exec(CPUArchState *cpustate, uint8_t *tb_ptr) t2 = tci_read_ri32(&tb_ptr); tci_write_reg32(t0, (t1 >> t2) | (t1 << (32 - t2))); break; +#endif +#if TCG_TARGET_HAS_deposit_i32 + case INDEX_op_deposit_i32: + t0 = *tb_ptr++; + t1 = tci_read_r32(&tb_ptr); + t2 = tci_read_r32(&tb_ptr); + tmp16 = *tb_ptr++; + tmp8 = *tb_ptr++; + tmp32 = (((1 << tmp8) - 1) << tmp16); + tci_write_reg32(t0, (t1 & ~tmp32) | ((t2 << tmp16) & tmp32)); + break; #endif case INDEX_op_brcond_i32: t0 = tci_read_r32(&tb_ptr); @@ -935,6 +946,17 @@ tcg_target_ulong tcg_qemu_tb_exec(CPUArchState *cpustate, uint8_t *tb_ptr) case INDEX_op_rotr_i64: TODO(); break; +#endif +#if TCG_TARGET_HAS_deposit_i64 + case INDEX_op_deposit_i64: + t0 = *tb_ptr++; + t1 = tci_read_r64(&tb_ptr); + t2 = tci_read_r64(&tb_ptr); + tmp16 = *tb_ptr++; + tmp8 = *tb_ptr++; + tmp64 = (((1ULL << tmp8) - 1) << tmp16); + tci_write_reg64(t0, (t1 & ~tmp64) | ((t2 << tmp16) & tmp64)); + break; #endif case INDEX_op_brcond_i64: t0 = tci_read_r64(&tb_ptr); -- cgit v1.2.1