Unsolved issues/bugs in the mips/mipsel backend
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- MIPS64:
  - No 64bit TLB support
  - no 64bit wide registers for FPU
  - 64bit mul/div handling broken
  - DM[FT]C not implemented

- TLB fails cornercase at address wrap around
- [ls][dw][lr] report broken (aligned) BadVAddr
- Missing per-CPU instruction decoding, currently all implemented
  instructions are regarded as valid
- pcnet32 does not work for little endian emulation on big endian host
  (probably not mips specific, but observable for mips-malta)

- We fake firmware support instead of doing the real thing