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authorPeter Wu <peter@lekensteyn.nl>2016-12-12 13:25:13 +0100
committerPeter Wu <peter@lekensteyn.nl>2016-12-12 13:25:13 +0100
commit011c56b0267a51f4c67e93c2fedbaa95782c484b (patch)
tree175d587f8e3a09c23367ddc72f497627d2a16698 /chip_design
parent405549ccd17c5d2709eccef65b1faa228dfad682 (diff)
download2IMF25-AR-011c56b0267a51f4c67e93c2fedbaa95782c484b.tar.gz
ChipDesign: Working solution
Diffstat (limited to 'chip_design')
-rwxr-xr-xchip_design/generate-chipdesign.py27
1 files changed, 21 insertions, 6 deletions
diff --git a/chip_design/generate-chipdesign.py b/chip_design/generate-chipdesign.py
index 23328ae..ca2f229 100755
--- a/chip_design/generate-chipdesign.py
+++ b/chip_design/generate-chipdesign.py
@@ -113,13 +113,28 @@ for i in range(len(powers), len(all_components)):
# (note: copied from above overlap check with '>='/'<=' -> '='.)
# Additionally: to "hit" the power resource over the X axis, an
# component Y coordinate must be within the power resource.
- # FIXME need to check whether there is an overlap
- pr_range = ' (>= x{j} )'
altpreds += fillin([
- '(and (= (+ y{j} h{j}) y{i})'' )',
- '(and (= (+ x{j} w{j}) x{i})'' )',
- '(and (= y{j} (+ y{i} h{i}))'' )',
- '(and (= x{j} (+ x{i} w{i}))'' )',
+ # Must have matching Y values and X in range.
+ # Assume that power resource is smaller than all others, so we do
+ # not need to check the case where the ends of a component is within
+ # the power component.
+ '(and ',
+ ' (or (= (+ y{j} h{j}) y{i})'
+ ' (= y{j} (+ y{i} h{i})))',
+ ' (or',
+ ' (and (<= x{i} x{j}) (<= x{j} (+ x{i} w{i})))',
+ ' (and (<= x{i} (+ x{j} w{j})) (<= (+ x{j} w{j}) (+ x{i} w{i})))',
+ ' )',
+ ')',
+ # Must have matching X values and Y in range.
+ '(and ',
+ ' (or (= (+ x{j} w{j}) x{i})'
+ ' (= x{j} (+ x{i} w{i})))',
+ ' (or',
+ ' (and (<= y{i} y{j}) (<= y{j} (+ y{i} h{i})))',
+ ' (and (<= y{i} (+ y{j} h{j})) (<= (+ y{j} h{j}) (+ y{i} h{i})))',
+ ' )',
+ ')',
], vars())
preds += ['(or %s)' % ' \n'.join(altpreds)]