From bf32a02e180a030307f7bc27896976abeaeb2c1a Mon Sep 17 00:00:00 2001
From: Peter Wu <peter@lekensteyn.nl>
Date: Mon, 12 Dec 2016 00:45:30 +0100
Subject: ChipDesign: attempt at hitting the power resource

---
 chip_design/generate-chipdesign.py | 15 +++++++++++++++
 chip_design/solution-to-latex.py   |  2 +-
 2 files changed, 16 insertions(+), 1 deletion(-)

(limited to 'chip_design')

diff --git a/chip_design/generate-chipdesign.py b/chip_design/generate-chipdesign.py
index 862053e..d834078 100755
--- a/chip_design/generate-chipdesign.py
+++ b/chip_design/generate-chipdesign.py
@@ -104,6 +104,21 @@ for i in range(len(powers)):
         ]
         preds += ['(or %s)' % ' '.join(fillin(altpreds, vars()))]
 
+# Require that each component is attached to power resource
+for i in range(len(powers), len(all_components)):
+    altpreds = []
+    for j in range(len(powers)):
+        # Power (j) top/right side hits component (i) bottom/left side or
+        # Power (j) bottom/left side hits component (i) top/right side.
+        # (note: copied from above overlap check with '>='/'<=' -> '='.)
+        altpreds += fillin([
+            '(= (+ y{j} h{j}) y{i})',
+            '(= (+ x{j} w{j}) x{i})',
+            '(= y{j} (+ y{i} h{i}))',
+            '(= x{j} (+ x{i} w{i}))',
+        ], vars())
+    preds += ['(or %s)' % ' \n'.join(altpreds)]
+
 # Begin generator
 s = """(benchmark test.smt
 :logic QF_UFLIA
diff --git a/chip_design/solution-to-latex.py b/chip_design/solution-to-latex.py
index aec9948..2028b1b 100755
--- a/chip_design/solution-to-latex.py
+++ b/chip_design/solution-to-latex.py
@@ -71,7 +71,7 @@ def print_boxes():
         attrs = ','.join(attrs)
 
         # For easier detection, reduce box dimension (add margin)
-        margin = 0.1
+        margin = 0.01
         x += margin
         y += margin
         x2 -= margin
-- 
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