diff options
author | Peter Wu <lekensteyn@gmail.com> | 2011-12-02 20:28:29 +0000 |
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committer | Peter Wu <lekensteyn@gmail.com> | 2011-12-02 20:28:29 +0000 |
commit | d48fb25678e10c79bf8971892b8573fb7cb9e247 (patch) | |
tree | 61138630c541427793ff40bbc1c1e342539f7328 /AsmLine.py | |
parent | a6f9617bd891074bba20cc1fc220e60a226e7fb4 (diff) | |
download | pp2cc-d48fb25678e10c79bf8971892b8573fb7cb9e247.tar.gz |
Use DW instead of DS, add ASM source, fix some coding errors
Diffstat (limited to 'AsmLine.py')
-rw-r--r-- | AsmLine.py | 15 |
1 files changed, 8 insertions, 7 deletions
@@ -47,25 +47,25 @@ class AsmLine(object): line = label + ":" + line parts = self.re_whitespace.split(line, 1) - instruction = parts[0] + self.instruction = parts[0] - if instruction in Asm.operators_binary: + if self.instruction in Asm.operators_binary: # a label for sure reg, operand = self.re_whitespace.split(parts[1], 1) self.register = reg self.setOperand(operand) - elif instruction in Asm.operators_branch: + elif self.instruction in Asm.operators_branch: # skip validation of reg for speed self.register = parts[1] - elif instruction in Asm.operators_unary: + elif self.instruction in Asm.operators_unary: self.setOperand(parts[1]) - elif instruction in Asm.operators_misc_reg: + elif self.instruction in Asm.operators_misc_reg: self.register = parts[1] - elif instruction in Asm.operators_misc_noreg: + elif self.instruction in Asm.operators_misc_noreg: # no args pass else: - raise RuntimeError("Unknown instruction '{}'".format(instruction)) + raise RuntimeError("Unknown instruction '{}'".format(self.instruction)) def setOperand(self, str): """Sets the operand for this object either as a string or an identifier object @@ -112,3 +112,4 @@ class AsmLine(object): if self.operand: # join all operand parts together line += " " + "".join(str(elm) for elm in self.operand) + return line |