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-rwxr-xr-xpp2cc.py43
1 files changed, 19 insertions, 24 deletions
diff --git a/pp2cc.py b/pp2cc.py
index c2f5029..b154367 100755
--- a/pp2cc.py
+++ b/pp2cc.py
@@ -1,13 +1,8 @@
#!/usr/bin/env python
"""Compiles C into assembly for the practicum processor (PP2)
-All rights reserved, you may not redistribute or use this program without prior
-permission from Peter Wu or Xander Houtman. Use of this program is entirely
-your own risk. In no circumstances can the authors of this program be held
-responsible for any damage including, but not limited to, financial damage or
-data loss. Modification of this program is not allowed without prior
-permission. The generated output (assembly and messages) are not subject to
-this license.
+Copyright (C) 2011-2014 Peter Wu <lekensteyn@gmail.com>
+Licensed under the MIT license <http://opensource.org/licenses/MIT>.
"""
import sys, re, os, operator
@@ -20,12 +15,12 @@ from Variables import Variables, GlobalVariables
from AsmParser import AsmParser
__author__ = "Peter Wu"
-__copyright__ = "Copyright 2011, Peter Wu"
-__credits__ = ["Peter Wu", "Xander Houtman"]
-__license__ = "Proprietary"
+__copyright__ = "Copyright (C) 2011-2014 Peter Wu"
+__credits__ = ["Xander Houtman"]
+__license__ = "MIT"
__version__ = "1.0"
__maintainer__ = "Peter Wu"
-__email__ = "uwretep@gmail.com"
+__email__ = "lekensteyn@gmail.com"
class Logger(object):
def __init__(self):
@@ -270,7 +265,7 @@ class Parse(object):
def parseBinaryLogicalOp(self, linked_node):
"""Returns lines of assembly for a logical OR or AND operation
-
+
ASM for logical OR:
operand1
BEQ fal ; if operand1 is false
@@ -280,7 +275,7 @@ class Parse(object):
BRA end
fal:LOAD R0 0
end:NOOP
-
+
ASM for logical AND:
operand1
BNE tru ; if operand1 is true
@@ -403,7 +398,7 @@ class Parse(object):
return lines
def processShift(self, operator, reg_number, operand_shift, linked_node=None):
"""Returns lines for a shift expression
-
+
Keyword arguments:
operator -- Either >> for right shift or << for left shift
reg_number -- A register Rn containing the number to be shifted
@@ -435,7 +430,7 @@ class Parse(object):
lines.append(self.asm.binary_op("DIV", reg_number, 2))
mask = "%0" + (self.WORDSIZE - 1) * "1"
lines.append(self.asm.binary_op("AND", reg_number, mask))
-
+
# decrease shift count and finish if shift count <= 0
lines.append(self.asm.binary_op("SUB", reg_shift, 1))
lines.append(self.asm.branch_op("BLE", lbl_shift_end))
@@ -528,10 +523,10 @@ class Parse(object):
return lines
def parseUnaryOp(self, linked_node):
"""Returns lines of assembly for unary operators
-
+
Supported operators are logical negation, one's complement (bitwise
NOT), plus and minus
-
+
ASM for logical NOT:
operand
BEQ fal ; if operand is false
@@ -581,14 +576,14 @@ class Parse(object):
return lines
def parseTernaryOp(self, linked_node):
"""Returns lines of ASM for ternary operation cond?expr_true:expr_false
-
+
It looks very similar to an If expect that the return value is important
"""
linked_node.incrementLevel()
node = linked_node.node
lbl_el = self.uniqLbl("el") # else
lbl_end = self.uniqLbl("fi") # endif
-
+
lines = self.parseExpression(node.cond, linked_node)
lines.append(self.asm.branch_op("BEQ", lbl_el))
@@ -618,7 +613,7 @@ class Parse(object):
return lines
def convertInteger(self, value=None, node=None):
"""Returns a string of the value
-
+
For integers, the string returned is a base-10 number modulo WORDSIZE
"""
if value is None:
@@ -828,7 +823,7 @@ class Parse(object):
return lines
def parseFor(self, linked_node):
"""Returns ASM for a for loop
-
+
for (init; cond; next) { body; } is equivalent to:
init; while (cond) { body; next; }
Note that for (;;){} is allowed too which is equivalent to:
@@ -954,7 +949,7 @@ class Parse(object):
return lines
def parseLValue(self, linked_node, register="R0"):
"""Returns lines of ASM for a lvalue type.
-
+
It's assumed that register does not change to another one. If this is
changed in the future, please revisit all uses of it.
"""
@@ -1154,7 +1149,7 @@ class Parse(object):
print("case label does not reduce to an integer constant")
print(e)
raise
-
+
lines_cases.append(self.asm.binary_op("CMP", switch_reg, case_val))
lines_cases.append(self.asm.branch_op("BEQ", lbl_case))
lines_stmts.append(self.asm.noop(lbl_case))
@@ -1486,7 +1481,7 @@ Options:
try:
parse = Parse()
-
+
for filename in settings["input_files"]:
parse.loadFile(filename, use_cpp=settings["use_cpp"],
cpp_args=settings["cpp_args"])