From 134d1ee7aa3eca21d5dd697e7d405cd9424b9dd4 Mon Sep 17 00:00:00 2001 From: Peter Wu Date: Wed, 7 Dec 2011 12:37:06 +0000 Subject: Fix PSW flags after doing a divison/modulo operation --- pp2cc.py | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/pp2cc.py b/pp2cc.py index 232c581..60aaa48 100755 --- a/pp2cc.py +++ b/pp2cc.py @@ -396,6 +396,10 @@ class Parse(object): lines += self.processShift(node.op, reg_first, operand, linked_node) else: lines.append(self.asm.binary_op(op, reg_first, operand)) + # explicitly set the PSW words because DIV and MOD are stupid and set + # the Z flag depending on the remainder + if op in ("DIV", "MOD"): + lines.append(self.asm.binary_op("LOAD", reg_first, reg_first)) return lines def processShift(self, operator, reg_number, operand_shift, linked_node=None): """Returns lines for a shift expression -- cgit v1.2.1