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authorJussi Kivilinna <jussi.kivilinna@iki.fi>2013-12-12 13:56:13 +0200
committerJussi Kivilinna <jussi.kivilinna@iki.fi>2013-12-13 00:13:12 +0200
commit2e4253dc8eb512cd0e807360926dc6ba912c95b4 (patch)
tree6ea95c8c04aa2593ba8eb5b83ec3ad6b70121918 /src/hwf-x86.c
parent69a6d0f9562fcd26112a589318c13de66ce1700e (diff)
downloadlibgcrypt-2e4253dc8eb512cd0e807360926dc6ba912c95b4.tar.gz
SHA-512: Add AVX and AVX2 implementations for x86-64
* cipher/Makefile.am: Add 'sha512-avx-amd64.S' and 'sha512-avx2-bmi2-amd64.S'. * cipher/sha512-avx-amd64.S: New. * cipher/sha512-avx2-bmi2-amd64.S: New. * cipher/sha512.c (USE_AVX, USE_AVX2): New. (SHA512_CONTEXT) [USE_AVX]: Add 'use_avx'. (SHA512_CONTEXT) [USE_AVX2]: Add 'use_avx2'. (sha512_init, sha384_init) [USE_AVX]: Initialize 'use_avx'. (sha512_init, sha384_init) [USE_AVX2]: Initialize 'use_avx2'. [USE_AVX] (_gcry_sha512_transform_amd64_avx): New. [USE_AVX2] (_gcry_sha512_transform_amd64_avx2): New. (transform) [USE_AVX2]: Add call for AVX2 implementation. (transform) [USE_AVX]: Add call for AVX implementation. * configure.ac (HAVE_GCC_INLINE_ASM_BMI2): New check. (sha512): Add 'sha512-avx-amd64.lo' and 'sha512-avx2-bmi2-amd64.lo'. * doc/gcrypt.texi: Document 'intel-cpu' and 'intel-bmi2'. * src/g10lib.h (HWF_INTEL_CPU, HWF_INTEL_BMI2): New. * src/hwfeatures.c (hwflist): Add "intel-cpu" and "intel-bmi2". * src/hwf-x86.c (detect_x86_gnuc): Check for HWF_INTEL_CPU and HWF_INTEL_BMI2. -- Patch adds fast AVX and AVX2 implementation of SHA-512 by Intel Corporation. The assembly source is licensed under 3-clause BSD license, thus compatible with LGPL2.1+. Original source can be accessed at: http://www.intel.com/p/en_US/embedded/hwsw/technology/packet-processing#docs Implementation is described in white paper "Fast SHA512 Implementations on IntelĀ® Architecture Processors" http://www.intel.com/content/www/us/en/intelligent-systems/intel-technology/fast-sha512-implementat$ Note: AVX implementation uses SHLD instruction to emulate RORQ, since it's faster on Intel Sandy-Bridge. However, on non-Intel CPUs SHLD is much slower than RORQ, so therefore AVX implementation is (for now) limited to Intel CPUs. Note: AVX2 implementation also uses BMI2 instruction rorx, thus additional HWF flag. Benchmarks: cpu Old SSSE3 AVX/AVX2 Old vs AVX/AVX2 vs SSSE3 Intel i5-4570 10.11 c/B 7.56 c/B 6.72 c/B 1.50x 1.12x Intel i5-2450M 14.11 c/B 10.53 c/B 8.88 c/B 1.58x 1.18x Signed-off-by: Jussi Kivilinna <jussi.kivilinna@iki.fi>
Diffstat (limited to 'src/hwf-x86.c')
-rw-r--r--src/hwf-x86.c7
1 files changed, 6 insertions, 1 deletions
diff --git a/src/hwf-x86.c b/src/hwf-x86.c
index ab6dacdc..4e825588 100644
--- a/src/hwf-x86.c
+++ b/src/hwf-x86.c
@@ -189,6 +189,7 @@ detect_x86_gnuc (void)
else if (!strcmp (vendor_id, "GenuineIntel"))
{
/* This is an Intel CPU. */
+ result |= HWF_INTEL_CPU;
}
else if (!strcmp (vendor_id, "AuthenticAMD"))
{
@@ -231,10 +232,14 @@ detect_x86_gnuc (void)
* Source: http://www.sandpile.org/x86/cpuid.htm */
if (max_cpuid_level >= 7 && (features & 0x00000001))
{
-#ifdef ENABLE_AVX2_SUPPORT
/* Get CPUID:7 contains further Intel feature flags. */
get_cpuid(7, NULL, &features, NULL, NULL);
+ /* Test bit 8 for BMI2. */
+ if (features & 0x00000100)
+ result |= HWF_INTEL_BMI2;
+
+#ifdef ENABLE_AVX2_SUPPORT
/* Test bit 5 for AVX2. */
if (features & 0x00000020)
result |= HWF_INTEL_AVX2;