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| author | Jussi Kivilinna <jussi.kivilinna@iki.fi> | 2013-12-11 19:32:08 +0200 |
|---|---|---|
| committer | Jussi Kivilinna <jussi.kivilinna@iki.fi> | 2013-12-12 23:41:37 +0200 |
| commit | e1a3931263e67aacec3c0bfcaa86c7d1441d5c6a (patch) | |
| tree | e38a42a3222c07e83bf1e438e4d02092392fa221 /src | |
| parent | 5e1239b1e2948211ff2675f45cce2b28c3379cfb (diff) | |
| download | libgcrypt-e1a3931263e67aacec3c0bfcaa86c7d1441d5c6a.tar.gz | |
SHA-256: Add SSSE3 implementation for x86-64
* cipher/Makefile.am: Add 'sha256-ssse3-amd64.S'.
* cipher/sha256-ssse3-amd64.S: New.
* cipher/sha256.c (USE_SSSE3): New.
(SHA256_CONTEXT) [USE_SSSE3]: Add 'use_ssse3'.
(sha256_init, sha224_init) [USE_SSSE3]: Initialize 'use_ssse3'.
(transform): Rename to...
(_transform): This.
[USE_SSSE3] (_gcry_sha256_transform_amd64_ssse3): New.
(transform): New.
* configure.ac (HAVE_INTEL_SYNTAX_PLATFORM_AS): New check.
(sha256): Add 'sha256-ssse3-amd64.lo'.
* doc/gcrypt.texi: Document 'intel-ssse3'.
* src/g10lib.h (HWF_INTEL_SSSE3): New.
* src/hwfeatures.c (hwflist): Add "intel-ssse3".
* src/hwf-x86.c (detect_x86_gnuc): Test for SSSE3.
--
Patch adds fast SSSE3 implementation of SHA-256 by Intel Corporation. The
assembly source is licensed under 3-clause BSD license, thus compatible
with LGPL2.1+. Original source can be accessed at:
http://www.intel.com/p/en_US/embedded/hwsw/technology/packet-processing#docs
Implementation is described in white paper
"Fast SHA - 256 Implementations on Intel® Architecture Processors"
http://www.intel.com/content/www/us/en/intelligent-systems/intel-technology/sha-256-implementations-paper.html
Benchmarks:
cpu Old New Diff
Intel i5-4570 13.99 c/B 10.66 c/B 1.31x
Intel i5-2450M 21.53 c/B 15.79 c/B 1.36x
Intel Core2 T8100 20.84 c/B 15.07 c/B 1.38x
Signed-off-by: Jussi Kivilinna <jussi.kivilinna@iki.fi>
Diffstat (limited to 'src')
| -rw-r--r-- | src/g10lib.h | 1 | ||||
| -rw-r--r-- | src/hwf-x86.c | 3 | ||||
| -rw-r--r-- | src/hwfeatures.c | 1 |
3 files changed, 5 insertions, 0 deletions
diff --git a/src/g10lib.h b/src/g10lib.h index 1e58ef69..6b2bafba 100644 --- a/src/g10lib.h +++ b/src/g10lib.h @@ -197,6 +197,7 @@ int _gcry_log_verbosity( int level ); #define HWF_PADLOCK_SHA 4 #define HWF_PADLOCK_MMUL 8 +#define HWF_INTEL_SSSE3 64 #define HWF_INTEL_PCLMUL 128 #define HWF_INTEL_AESNI 256 #define HWF_INTEL_RDRAND 512 diff --git a/src/hwf-x86.c b/src/hwf-x86.c index 784fe2a4..ab6dacdc 100644 --- a/src/hwf-x86.c +++ b/src/hwf-x86.c @@ -206,6 +206,9 @@ detect_x86_gnuc (void) if (features & 0x00000002) result |= HWF_INTEL_PCLMUL; #endif + /* Test bit 9 for SSSE3. */ + if (features & 0x00000200) + result |= HWF_INTEL_SSSE3; #ifdef ENABLE_AESNI_SUPPORT /* Test bit 25 for AES-NI. */ if (features & 0x02000000) diff --git a/src/hwfeatures.c b/src/hwfeatures.c index 66998167..5c3bb182 100644 --- a/src/hwfeatures.c +++ b/src/hwfeatures.c @@ -46,6 +46,7 @@ static struct { HWF_PADLOCK_AES, "padlock-aes" }, { HWF_PADLOCK_SHA, "padlock-sha" }, { HWF_PADLOCK_MMUL,"padlock-mmul"}, + { HWF_INTEL_SSSE3, "intel-ssse3" }, { HWF_INTEL_PCLMUL,"intel-pclmul" }, { HWF_INTEL_AESNI, "intel-aesni" }, { HWF_INTEL_RDRAND,"intel-rdrand" }, |