diff options
| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2018-02-08 13:48:18 -0300 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2018-02-13 16:15:09 +0100 |
| commit | 1e23b63f022ae79d7a5c535fe549127ad52d5ba6 (patch) | |
| tree | 16716c50209daf6f80e78d0e8f1290b864ccccd3 | |
| parent | f18e6d50e2b42410699ccffcf42d5c420bc5302b (diff) | |
| download | qemu-1e23b63f022ae79d7a5c535fe549127ad52d5ba6.tar.gz | |
sdhci: add Spec v4.2 register definitions
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20180208164818.7961-31-f4bug@amsat.org>
| -rw-r--r-- | hw/sd/sdhci-internal.h | 9 | ||||
| -rw-r--r-- | hw/sd/sdhci.c | 16 |
2 files changed, 24 insertions, 1 deletions
diff --git a/hw/sd/sdhci-internal.h b/hw/sd/sdhci-internal.h index 33e87680ed..756ef3f3c2 100644 --- a/hw/sd/sdhci-internal.h +++ b/hw/sd/sdhci-internal.h @@ -197,6 +197,10 @@ FIELD(SDHC_HOSTCTL2, V18_ENA, 3, 1); /* UHS-I only */ FIELD(SDHC_HOSTCTL2, DRIVER_STRENGTH, 4, 2); /* UHS-I only */ FIELD(SDHC_HOSTCTL2, EXECUTE_TUNING, 6, 1); /* UHS-I only */ FIELD(SDHC_HOSTCTL2, SAMPLING_CLKSEL, 7, 1); /* UHS-I only */ +FIELD(SDHC_HOSTCTL2, UHS_II_ENA, 8, 1); /* since v4 */ +FIELD(SDHC_HOSTCTL2, ADMA2_LENGTH, 10, 1); /* since v4 */ +FIELD(SDHC_HOSTCTL2, CMD23_ENA, 11, 1); /* since v4 */ +FIELD(SDHC_HOSTCTL2, VERSION4, 12, 1); /* since v4 */ FIELD(SDHC_HOSTCTL2, ASYNC_INT, 14, 1); FIELD(SDHC_HOSTCTL2, PRESET_ENA, 15, 1); @@ -215,10 +219,12 @@ FIELD(SDHC_CAPAB, SUSPRESUME, 23, 1); FIELD(SDHC_CAPAB, V33, 24, 1); FIELD(SDHC_CAPAB, V30, 25, 1); FIELD(SDHC_CAPAB, V18, 26, 1); +FIELD(SDHC_CAPAB, BUS64BIT_V4, 27, 1); /* since v4.10 */ FIELD(SDHC_CAPAB, BUS64BIT, 28, 1); /* since v2 */ FIELD(SDHC_CAPAB, ASYNC_INT, 29, 1); /* since v3 */ FIELD(SDHC_CAPAB, SLOT_TYPE, 30, 2); /* since v3 */ FIELD(SDHC_CAPAB, BUS_SPEED, 32, 3); /* since v3 */ +FIELD(SDHC_CAPAB, UHS_II, 35, 8); /* since v4.20 */ FIELD(SDHC_CAPAB, DRIVER_STRENGTH, 36, 3); /* since v3 */ FIELD(SDHC_CAPAB, DRIVER_TYPE_A, 36, 1); /* since v3 */ FIELD(SDHC_CAPAB, DRIVER_TYPE_C, 37, 1); /* since v3 */ @@ -227,12 +233,15 @@ FIELD(SDHC_CAPAB, TIMER_RETUNING, 40, 4); /* since v3 */ FIELD(SDHC_CAPAB, SDR50_TUNING, 45, 1); /* since v3 */ FIELD(SDHC_CAPAB, RETUNING_MODE, 46, 2); /* since v3 */ FIELD(SDHC_CAPAB, CLOCK_MULT, 48, 8); /* since v3 */ +FIELD(SDHC_CAPAB, ADMA3, 59, 1); /* since v4.20 */ +FIELD(SDHC_CAPAB, V18_VDD2, 60, 1); /* since v4.20 */ /* HWInit Maximum Current Capabilities Register 0x0 */ #define SDHC_MAXCURR 0x48 FIELD(SDHC_MAXCURR, V33_VDD1, 0, 8); FIELD(SDHC_MAXCURR, V30_VDD1, 8, 8); FIELD(SDHC_MAXCURR, V18_VDD1, 16, 8); +FIELD(SDHC_MAXCURR, V18_VDD2, 32, 8); /* since v4.20 */ /* W Force Event Auto CMD12 Error Interrupt Register 0x0000 */ #define SDHC_FEAER 0x50 diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index 1a6771be4e..97b4a473c8 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -91,6 +91,20 @@ static void sdhci_check_capareg(SDHCIState *s, Error **errp) bool y; switch (s->sd_spec_version) { + case 4: + val = FIELD_EX64(s->capareg, SDHC_CAPAB, BUS64BIT_V4); + trace_sdhci_capareg("64-bit system bus (v4)", val); + msk = FIELD_DP64(msk, SDHC_CAPAB, BUS64BIT_V4, 0); + + val = FIELD_EX64(s->capareg, SDHC_CAPAB, UHS_II); + trace_sdhci_capareg("UHS-II", val); + msk = FIELD_DP64(msk, SDHC_CAPAB, UHS_II, 0); + + val = FIELD_EX64(s->capareg, SDHC_CAPAB, ADMA3); + trace_sdhci_capareg("ADMA3", val); + msk = FIELD_DP64(msk, SDHC_CAPAB, ADMA3, 0); + + /* fallthrough */ case 3: val = FIELD_EX64(s->capareg, SDHC_CAPAB, ASYNC_INT); trace_sdhci_capareg("async interrupt", val); @@ -145,7 +159,7 @@ static void sdhci_check_capareg(SDHCIState *s, Error **errp) msk = FIELD_DP64(msk, SDHC_CAPAB, ADMA1, 0); val = FIELD_EX64(s->capareg, SDHC_CAPAB, BUS64BIT); - trace_sdhci_capareg("64-bit system bus", val); + trace_sdhci_capareg("64-bit system bus (v3)", val); msk = FIELD_DP64(msk, SDHC_CAPAB, BUS64BIT, 0); /* fallthrough */ |