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| author | Eduardo Habkost <ehabkost@redhat.com> | 2015-03-13 15:39:43 -0300 |
|---|---|---|
| committer | Eduardo Habkost <ehabkost@redhat.com> | 2015-03-19 16:35:14 -0300 |
| commit | 1ee9159882f6687d6bc1f2207e97ada1eeccaa7c (patch) | |
| tree | 32ba4168a5beda9a267e78ac3168d5cae3b33564 | |
| parent | 3e5f6234b4f45a11b7c357dde2d6da36641bc6f6 (diff) | |
| download | qemu-1ee9159882f6687d6bc1f2207e97ada1eeccaa7c.tar.gz | |
Revert "target-i386: Disable HLE and RTM on Haswell & Broadwell"
This reverts commit 13704e4c455770d500d6b87b117e32f0d01252c9.
With the Intel microcode update that removed HLE and RTM, there will be
different kinds of Haswell and Broadwell CPUs out there: some that still
have the HLE and RTM features, and some that don't have the HLE and RTM
features. On both cases people may be willing to use the pc-*-2.3
machine-types.
So instead of making the CPU model results confusing by making it depend
on the machine-type, keep HLE and RTM on the existing Haswell and
Broadwell CPU models. The plan is to introduce "Haswell-noTSX" and
"Broadwell-noTSX" CPU models later, for people who have CPUs that don't
have TSX feature available.
Reviewed-by: Daniel P. Berrange <berrange@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
| -rw-r--r-- | hw/i386/pc_piix.c | 4 | ||||
| -rw-r--r-- | hw/i386/pc_q35.c | 4 | ||||
| -rw-r--r-- | target-i386/cpu.c | 9 |
3 files changed, 5 insertions, 12 deletions
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 36c69d71ef..1fe7bfb29a 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -331,10 +331,6 @@ static void pc_compat_2_2(MachineState *machine) x86_cpu_compat_set_features("Haswell", FEAT_1_ECX, 0, CPUID_EXT_RDRAND); x86_cpu_compat_set_features("Broadwell", FEAT_1_ECX, 0, CPUID_EXT_F16C); x86_cpu_compat_set_features("Broadwell", FEAT_1_ECX, 0, CPUID_EXT_RDRAND); - x86_cpu_compat_set_features("Haswell", FEAT_7_0_EBX, - CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_RTM, 0); - x86_cpu_compat_set_features("Broadwell", FEAT_7_0_EBX, - CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_RTM, 0); machine->suppress_vmdesc = true; } diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index bc40537d55..dcc17c074b 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -310,10 +310,6 @@ static void pc_compat_2_2(MachineState *machine) x86_cpu_compat_set_features("Haswell", FEAT_1_ECX, 0, CPUID_EXT_RDRAND); x86_cpu_compat_set_features("Broadwell", FEAT_1_ECX, 0, CPUID_EXT_F16C); x86_cpu_compat_set_features("Broadwell", FEAT_1_ECX, 0, CPUID_EXT_RDRAND); - x86_cpu_compat_set_features("Haswell", FEAT_7_0_EBX, - CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_RTM, 0); - x86_cpu_compat_set_features("Broadwell", FEAT_7_0_EBX, - CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_RTM, 0); machine->suppress_vmdesc = true; } diff --git a/target-i386/cpu.c b/target-i386/cpu.c index f01690bfea..02def075df 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -1099,8 +1099,9 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_EXT3_LAHF_LM, .features[FEAT_7_0_EBX] = CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | - CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | - CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID, + CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | + CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | + CPUID_7_0_EBX_RTM, .features[FEAT_XSAVE] = CPUID_XSAVE_XSAVEOPT, .xlevel = 0x8000000A, @@ -1133,9 +1134,9 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, .features[FEAT_7_0_EBX] = CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | - CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | + CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | - CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | + CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP, .features[FEAT_XSAVE] = CPUID_XSAVE_XSAVEOPT, |