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authorCédric Le Goater <clg@kaod.org>2017-04-03 09:46:04 +0200
committerDavid Gibson <david@gibson.dropbear.id.au>2017-04-26 12:00:42 +1000
commit5509db4aec13217022d41b131c8216040fb723f1 (patch)
tree1598354b8bacb5cef523653764d5d4907c666207
parent960fbd29e56866ff7b1f2c6a24082774fd254bda (diff)
downloadqemu-5509db4aec13217022d41b131c8216040fb723f1.tar.gz
ppc/pnv: add a helper to calculate MMIO addresses registers
Some controllers (ICP, PSI) have a base register address which is calculated using the chip id. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
-rw-r--r--include/hw/ppc/pnv.h12
1 files changed, 11 insertions, 1 deletions
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index df98a72006..5693ba181d 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -91,14 +91,24 @@ typedef struct PnvChipClass {
OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER9)
/*
- * This generates a HW chip id depending on an index:
+ * This generates a HW chip id depending on an index, as found on a
+ * two socket system with dual chip modules :
*
* 0x0, 0x1, 0x10, 0x11
*
* 4 chips should be the maximum
+ *
+ * TODO: use a machine property to define the chip ids
*/
#define PNV_CHIP_HWID(i) ((((i) & 0x3e) << 3) | ((i) & 0x1))
+/*
+ * Converts back a HW chip id to an index. This is useful to calculate
+ * the MMIO addresses of some controllers which depend on the chip id.
+ */
+#define PNV_CHIP_INDEX(chip) \
+ (((chip)->chip_id >> 2) * 2 + ((chip)->chip_id & 0x3))
+
#define TYPE_POWERNV_MACHINE MACHINE_TYPE_NAME("powernv")
#define POWERNV_MACHINE(obj) \
OBJECT_CHECK(PnvMachineState, (obj), TYPE_POWERNV_MACHINE)