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| author | Edgar E. Iglesias <edgar.iglesias@xilinx.com> | 2018-04-14 18:06:34 +0200 |
|---|---|---|
| committer | Edgar E. Iglesias <edgar.iglesias@xilinx.com> | 2018-04-30 16:43:20 +0200 |
| commit | 59b1a90b0b5dc6b368364e9e1d40184eb4506c39 (patch) | |
| tree | 52ddaaf57e41a4d88eb928e0073a1686d2dacd79 | |
| parent | 6f0c4706b35dead265509115ddbd2a8d1af516c1 (diff) | |
| download | qemu-59b1a90b0b5dc6b368364e9e1d40184eb4506c39.tar.gz | |
target-microblaze: Respect MSR.PVR as read-only
Respect MSR.PVR as read-only. We were wrongly overwriting the PVR bit.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
| -rw-r--r-- | target/microblaze/translate.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 7628b0e25b..f739751930 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -424,7 +424,7 @@ static inline void msr_write(DisasContext *dc, TCGv v) /* PVR bit is not writable. */ tcg_gen_andi_tl(t, v, ~MSR_PVR); tcg_gen_andi_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], MSR_PVR); - tcg_gen_or_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], v); + tcg_gen_or_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], t); tcg_temp_free(t); } |