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| author | Peter Maydell <peter.maydell@linaro.org> | 2011-11-13 14:18:39 +0000 |
|---|---|---|
| committer | Andrzej Zaborowski <andrew.zaborowski@intel.com> | 2011-11-14 02:26:20 +0100 |
| commit | 7c64d297f988f6ee2136f29fac010db2c8fc352c (patch) | |
| tree | 6f4510e6a7b6ef9be6d4e3709439ee097c9a82e5 | |
| parent | e7852674d5013bffd0bb8e822a7521f76677a60b (diff) | |
| download | qemu-7c64d297f988f6ee2136f29fac010db2c8fc352c.tar.gz | |
hw/pxa2xx.c: Fix handling of RW bits in PMCR
Fix an error in commit afd4a6522 which meant that writing a zero
to the RW bits in the PMCR wouldn't actually clear them. (Error
spotted by Andrzej Zaborowski.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
| -rw-r--r-- | hw/pxa2xx.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/hw/pxa2xx.c b/hw/pxa2xx.c index d38b922924..e9a507ece5 100644 --- a/hw/pxa2xx.c +++ b/hw/pxa2xx.c @@ -117,6 +117,7 @@ static void pxa2xx_pm_write(void *opaque, target_phys_addr_t addr, /* Clear the write-one-to-clear bits... */ s->pm_regs[addr >> 2] &= ~(value & 0x2a); /* ...and set the plain r/w bits */ + s->pm_regs[addr >> 2] &= ~0x15; s->pm_regs[addr >> 2] |= value & 0x15; break; |