diff options
| author | BALATON Zoltan <balaton@eik.bme.hu> | 2018-03-26 01:54:28 +0200 |
|---|---|---|
| committer | David Gibson <david@gibson.dropbear.id.au> | 2018-04-27 18:05:22 +1000 |
| commit | 99d45f8fbd6756c2495bcb554dcbf50585f1f7b0 (patch) | |
| tree | f1f862efeda73aa98059ab4ffa2cf97843cf1c2c | |
| parent | a2f04333a340282c0842e76c055297cb7ba56f0f (diff) | |
| download | qemu-99d45f8fbd6756c2495bcb554dcbf50585f1f7b0.tar.gz | |
target/ppc: Fix reserved bit mask of dstst instruction
According to the Vector/SIMD extension documentation bit 6 that is
currently masked is valid (listed as transient bit) but bits 7 and 8
should be reserved instead. Fix the mask to match this.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
| -rw-r--r-- | target/ppc/translate.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 3457d29f8e..b0d79a3fb9 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -6561,7 +6561,7 @@ GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE), GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), -GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC), +GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC), GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA), |