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authorStefan Weil <weil@mail.berlios.de>2011-04-30 22:49:26 +0200
committerStefan Hajnoczi <stefanha@linux.vnet.ibm.com>2011-05-22 22:31:45 +0100
commita57d23e4f7e7e81c839a7b53a973ac71eefe91da (patch)
treea09096b2adee4d1c4dbac958654bc9898a27587a
parent39e594dbcd897849f2ca95b3310ea00fff29ea99 (diff)
downloadqemu-a57d23e4f7e7e81c839a7b53a973ac71eefe91da.tar.gz
Fix typos in comments (chek -> check)
Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
-rw-r--r--exec.c2
-rw-r--r--target-ppc/STATUS2
2 files changed, 2 insertions, 2 deletions
diff --git a/exec.c b/exec.c
index a6df2d6139..563e9743f9 100644
--- a/exec.c
+++ b/exec.c
@@ -2061,7 +2061,7 @@ void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end,
/* we modify the TLB cache so that the dirty bit will be set again
when accessing the range */
start1 = (unsigned long)qemu_safe_ram_ptr(start);
- /* Chek that we don't span multiple blocks - this breaks the
+ /* Check that we don't span multiple blocks - this breaks the
address comparisons below. */
if ((unsigned long)qemu_safe_ram_ptr(end - 1) - start1
!= (end - 1) - start) {
diff --git a/target-ppc/STATUS b/target-ppc/STATUS
index 32e7ffa493..c8e9018bfc 100644
--- a/target-ppc/STATUS
+++ b/target-ppc/STATUS
@@ -11,7 +11,7 @@ INSN: instruction set.
SPR: special purpose registers set
OK => all SPR registered (but some may be fake)
KO => some SPR are missing or should be removed
- ? => uncheked
+ ? => unchecked
MSR: MSR bits definitions
OK => all MSR bits properly defined
KO => MSR definition is incorrect