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| author | Peter Maydell <peter.maydell@linaro.org> | 2017-04-25 14:48:53 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2017-04-25 14:48:55 +0100 |
| commit | fe491fa85c4634453b340b18046aae2eaf8147db (patch) | |
| tree | d0b7f669f4e422ab6046762bd0408c430d4b1768 | |
| parent | b8c7193fe9479a941a56863595766d4517152dae (diff) | |
| parent | 2cf9953beebd194a432ebd567399807d9b1f6a4d (diff) | |
| download | qemu-fe491fa85c4634453b340b18046aae2eaf8147db.tar.gz | |
Merge remote-tracking branch 'remotes/agraf/tags/signed-s390-for-upstream' into staging
Patch queue for s390 - 2017-04-25
Two simple fixes this time around:
- fix BQL for s390 virtio target
- Fix SIGP emulation
# gpg: Signature made Tue 25 Apr 2017 12:40:38 BST
# gpg: using RSA key 0x2B33791E03FEDC60
# gpg: Good signature from "Alexander Graf <agraf@suse.de>"
# gpg: aka "Alexander Graf <alex@csgraf.de>"
# Primary key fingerprint: 7F2A 4C87 F94C 5EFE DBC3 75DC 1631 30DA 5B24 530A
# Subkey fingerprint: 54D3 364F A6C3 60FF AF81 EB53 2B33 791E 03FE DC60
* remotes/agraf/tags/signed-s390-for-upstream:
s390x/misc_helper.c: wrap s390_virtio_hypercall in BQL
target-s390x: Mask the SIGP order_code to 8bit.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | target/s390x/misc_helper.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/target/s390x/misc_helper.c b/target/s390x/misc_helper.c index 93b0e61366..eca82441d0 100644 --- a/target/s390x/misc_helper.c +++ b/target/s390x/misc_helper.c @@ -288,7 +288,9 @@ void HELPER(diag)(CPUS390XState *env, uint32_t r1, uint32_t r3, uint32_t num) switch (num) { case 0x500: /* KVM hypercall */ + qemu_mutex_lock_iothread(); r = s390_virtio_hypercall(env); + qemu_mutex_unlock_iothread(); break; case 0x44: /* yield */ @@ -515,7 +517,8 @@ uint32_t HELPER(sigp)(CPUS390XState *env, uint64_t order_code, uint32_t r1, /* Remember: Use "R1 or R1 + 1, whichever is the odd-numbered register" as parameter (input). Status (output) is always R1. */ - switch (order_code) { + /* sigp contains the order code in bit positions 56-63, mask it here. */ + switch (order_code & 0xff) { case SIGP_SET_ARCH: /* switch arch */ break; |