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authorPranith Kumar <bobby.prani@gmail.com>2017-08-29 02:33:12 -0400
committerRichard Henderson <richard.henderson@linaro.org>2017-09-05 13:41:46 -0700
commitb32dc3370a666e237b2099c22166b15e58cb6df8 (patch)
tree42968d38c5eab9f9c2f30bb74cf8b874fed49942 /disas
parent71650df7b0ee0600308810a267a123b971b3d533 (diff)
downloadqemu-b32dc3370a666e237b2099c22166b15e58cb6df8.tar.gz
tcg: Implement implicit ordering semantics
Currently, we cannot use mttcg for running strong memory model guests on weak memory model hosts due to missing ordering semantics. We implicitly generate fence instructions for stronger guests if an ordering mismatch is detected. We generate fences only for the orders for which fence instructions are necessary, for example a fence is not necessary between a store and a subsequent load on x86 since its absence in the guest binary tells that ordering need not be ensured. Also note that if we find multiple subsequent fence instructions in the generated IR, we combine them in the TCG optimization pass. This patch allows us to boot an x86 guest on ARM64 hosts using mttcg. Signed-off-by: Pranith Kumar <bobby.prani@gmail.com> Message-Id: <20170829063313.10237-4-bobby.prani@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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