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| author | Avi Kivity <avi@redhat.com> | 2011-08-08 16:09:17 +0300 |
|---|---|---|
| committer | Anthony Liguori <aliguori@us.ibm.com> | 2011-08-08 10:22:29 -0500 |
| commit | 23c5e4cab2d64e00b6000f4a360c87f65e003545 (patch) | |
| tree | f3f792022ceee91b5b7df261534d94370b72aef1 /hw/ppc_mac.h | |
| parent | b0ce84e50bd232db4f6fb0f3572d2e274d1787b0 (diff) | |
| download | qemu-23c5e4cab2d64e00b6000f4a360c87f65e003545.tar.gz | |
ppc: convert to memory API
Reviewed-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Anthony Liguori <aliguori@us.ibm.com>
Signed-off-by: Avi Kivity <avi@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Diffstat (limited to 'hw/ppc_mac.h')
| -rw-r--r-- | hw/ppc_mac.h | 16 |
1 files changed, 9 insertions, 7 deletions
diff --git a/hw/ppc_mac.h b/hw/ppc_mac.h index 25a227483f..7351bb6d37 100644 --- a/hw/ppc_mac.h +++ b/hw/ppc_mac.h @@ -42,15 +42,16 @@ #define ESCC_CLOCK 3686400 /* Cuda */ -void cuda_init (int *cuda_mem_index, qemu_irq irq); +void cuda_init (MemoryRegion **cuda_mem, qemu_irq irq); /* MacIO */ -void macio_init (PCIBus *bus, int device_id, int is_oldworld, int pic_mem_index, - int dbdma_mem_index, int cuda_mem_index, void *nvram, - int nb_ide, int *ide_mem_index, int escc_mem_index); +void macio_init (PCIBus *bus, int device_id, int is_oldworld, + MemoryRegion *pic_mem, MemoryRegion *dbdma_mem, + MemoryRegion *cuda_mem, void *nvram, + int nb_ide, MemoryRegion **ide_mem, MemoryRegion *escc_mem); /* Heathrow PIC */ -qemu_irq *heathrow_pic_init(int *pmem_index, +qemu_irq *heathrow_pic_init(MemoryRegion **pmem, int nb_cpus, qemu_irq **irqs); /* Grackle PCI */ @@ -69,9 +70,10 @@ PCIBus *pci_pmac_u3_init(qemu_irq *pic, /* Mac NVRAM */ typedef struct MacIONVRAMState MacIONVRAMState; -MacIONVRAMState *macio_nvram_init (int *mem_index, target_phys_addr_t size, +MacIONVRAMState *macio_nvram_init (target_phys_addr_t size, unsigned int it_shift); -void macio_nvram_map (void *opaque, target_phys_addr_t mem_base); +void macio_nvram_setup_bar(MacIONVRAMState *s, MemoryRegion *bar, + target_phys_addr_t mem_base); void pmac_format_nvram_partition (MacIONVRAMState *nvr, int len); uint32_t macio_nvram_read (void *opaque, uint32_t addr); void macio_nvram_write (void *opaque, uint32_t addr, uint32_t val); |