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authorbalrog <balrog@c046a42c-6fe2-441c-8c8c-71466251a162>2007-05-08 19:03:12 +0000
committerbalrog <balrog@c046a42c-6fe2-441c-8c8c-71466251a162>2007-05-08 19:03:12 +0000
commitd95b2f8d365a3ef431111e9188d219de1f577a90 (patch)
tree218856598a07ffa4ef0bfac361738c8c7881b847 /hw/pxa2xx.c
parentce8198612e08f737057d9984a9fa1bf18af8ce4b (diff)
downloadqemu-d95b2f8d365a3ef431111e9188d219de1f577a90.tar.gz
Switch to qemu_ram_alloc() for memory allocation in PXA255/270.
Pass correct RAM size to arm_load_kernel (currently unused) - thanks to BobOfDoom. Register the Xscale Internal Memory Storage. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2784 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'hw/pxa2xx.c')
-rw-r--r--hw/pxa2xx.c18
1 files changed, 16 insertions, 2 deletions
diff --git a/hw/pxa2xx.c b/hw/pxa2xx.c
index 9f4c46c683..19494b88be 100644
--- a/hw/pxa2xx.c
+++ b/hw/pxa2xx.c
@@ -1515,7 +1515,8 @@ void pxa2xx_reset(int line, int level, void *opaque)
}
/* Initialise a PXA270 integrated chip (ARM based core). */
-struct pxa2xx_state_s *pxa270_init(DisplayState *ds, const char *revision)
+struct pxa2xx_state_s *pxa270_init(unsigned int sdram_size,
+ DisplayState *ds, const char *revision)
{
struct pxa2xx_state_s *s;
struct pxa2xx_ssp_s *ssp;
@@ -1530,6 +1531,12 @@ struct pxa2xx_state_s *pxa270_init(DisplayState *ds, const char *revision)
s->env = cpu_init();
cpu_arm_set_model(s->env, revision ?: "pxa270");
+ /* SDRAM & Internal Memory Storage */
+ cpu_register_physical_memory(PXA2XX_SDRAM_BASE,
+ sdram_size, qemu_ram_alloc(sdram_size) | IO_MEM_RAM);
+ cpu_register_physical_memory(PXA2XX_INTERNAL_BASE,
+ 0x40000, qemu_ram_alloc(0x40000) | IO_MEM_RAM);
+
s->pic = pxa2xx_pic_init(0x40d00000, s->env);
s->dma = pxa27x_dma_init(0x40000000, s->pic[PXA2XX_PIC_DMA]);
@@ -1613,7 +1620,8 @@ struct pxa2xx_state_s *pxa270_init(DisplayState *ds, const char *revision)
}
/* Initialise a PXA255 integrated chip (ARM based core). */
-struct pxa2xx_state_s *pxa255_init(DisplayState *ds)
+struct pxa2xx_state_s *pxa255_init(unsigned int sdram_size,
+ DisplayState *ds)
{
struct pxa2xx_state_s *s;
struct pxa2xx_ssp_s *ssp;
@@ -1623,6 +1631,12 @@ struct pxa2xx_state_s *pxa255_init(DisplayState *ds)
s->env = cpu_init();
cpu_arm_set_model(s->env, "pxa255");
+ /* SDRAM & Internal Memory Storage */
+ cpu_register_physical_memory(PXA2XX_SDRAM_BASE,
+ sdram_size, qemu_ram_alloc(sdram_size) | IO_MEM_RAM);
+ cpu_register_physical_memory(PXA2XX_INTERNAL_BASE,
+ 0x40000, qemu_ram_alloc(0x40000) | IO_MEM_RAM);
+
s->pic = pxa2xx_pic_init(0x40d00000, s->env);
s->dma = pxa255_dma_init(0x40000000, s->pic[PXA2XX_PIC_DMA]);