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| author | Peter Maydell <peter.maydell@linaro.org> | 2016-01-21 14:15:08 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2016-01-21 14:15:08 +0000 |
| commit | 966f758c49ff478c4757efa5970ce649161bff92 (patch) | |
| tree | 29628262925876e608a318920e9150f65f991229 /target-arm/cpu-qom.h | |
| parent | f3a9b6945cbbb23f3a70da14e9ffdf1e60c580a8 (diff) | |
| download | qemu-966f758c49ff478c4757efa5970ce649161bff92.tar.gz | |
target-arm: Use a single entry point for AArch64 and AArch32 exceptions
If EL2 or EL3 is present on an AArch64 CPU, then exceptions can be
taken to an exception level which is running AArch32 (if only EL0
and EL1 are present then EL1 must be AArch64 and all exceptions are
taken to AArch64). To support this we need to have a single
implementation of the CPU do_interrupt() method which can handle both
32 and 64 bit exception entry.
Pull the common parts of aarch64_cpu_do_interrupt() and
arm_cpu_do_interrupt() out into a new function which calls
either the AArch32 or AArch64 specific entry code once it has
worked out which one is needed.
We temporarily special-case the handling of EXCP_SEMIHOST to
avoid an assertion in arm_el_is_aa64(); the next patch will
pull all the semihosting handling out to the arm_cpu_do_interrupt()
level (since semihosting semantics depend on the register width
of the calling code, not on that of any higher EL).
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Diffstat (limited to 'target-arm/cpu-qom.h')
| -rw-r--r-- | target-arm/cpu-qom.h | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h index 979e1ee4cf..07c0a71942 100644 --- a/target-arm/cpu-qom.h +++ b/target-arm/cpu-qom.h @@ -254,6 +254,4 @@ int aarch64_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); #endif -void aarch64_cpu_do_interrupt(CPUState *cs); - #endif |