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| author | Alistair Francis <alistair.francis@xilinx.com> | 2014-03-10 14:56:28 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2014-03-10 14:56:28 +0000 |
| commit | 7c2cb42b5033a851aa2a81de8d8a9e75bb65c2b6 (patch) | |
| tree | f2236275aa8f52c97c66ec6f07fd628abd6b4f33 /target-arm/cpu.h | |
| parent | af5199347a874db2214bf818151bad71b856ff37 (diff) | |
| download | qemu-7c2cb42b5033a851aa2a81de8d8a9e75bb65c2b6.tar.gz | |
target-arm: Implements the ARM PMCCNTR register
This patch implements the ARM PMCCNTR register including
the disable and reset components of the PMCR register.
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
Message-id: bbf405e1feaf352cf39d5db402c9efcbd0f57c78.1393459802.git.alistair.francis@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-arm/cpu.h')
| -rw-r--r-- | target-arm/cpu.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 49fef3fcbe..0a7edfe6cb 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -222,6 +222,10 @@ typedef struct CPUARMState { uint64_t dbgbcr[16]; /* breakpoint control registers */ uint64_t dbgwvr[16]; /* watchpoint value registers */ uint64_t dbgwcr[16]; /* watchpoint control registers */ + /* If the counter is enabled, this stores the last time the counter + * was reset. Otherwise it stores the counter value + */ + uint32_t c15_ccnt; } cp15; struct { |