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| author | bellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162> | 2005-04-17 19:16:13 +0000 |
|---|---|---|
| committer | bellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162> | 2005-04-17 19:16:13 +0000 |
| commit | 1fddef4b1ba3bf14d36472475019a4a6acd4d976 (patch) | |
| tree | 4cef1b563a49637d0bd0cacc5ec4c78c32e953de /target-arm/cpu.h | |
| parent | 6e4255f6a65091fbe7d17bfda546e2aa1b72f9a6 (diff) | |
| download | qemu-1fddef4b1ba3bf14d36472475019a4a6acd4d976.tar.gz | |
gdb support for user mode (Paul Brook)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1367 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-arm/cpu.h')
| -rw-r--r-- | target-arm/cpu.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 1346175134..ef7469d0c3 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -26,6 +26,8 @@ #include "softfloat.h" +#define TARGET_HAS_ICE 1 + #define EXCP_UDEF 1 /* undefined instruction */ #define EXCP_SWI 2 /* software interrupt */ #define EXCP_PREFETCH_ABORT 3 @@ -62,6 +64,11 @@ typedef struct CPUARMState { int user_mode_only; uint32_t address; + /* ICE debug support. */ + target_ulong breakpoints[MAX_BREAKPOINTS]; + int nb_breakpoints; + int singlestep_enabled; + /* in order to avoid passing too many arguments to the memory write helpers, we store some rarely used information in the CPU context) */ |