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| author | Greg Bellows <greg.bellows@linaro.org> | 2015-05-29 11:28:52 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2015-05-29 11:28:52 +0100 |
| commit | c6f191642a4027909813b4e6e288411f8371e951 (patch) | |
| tree | c2ad623d9938b41924b431ac4b381bf64bc5670c /target-arm/cpu.h | |
| parent | 38836a2cd47c20daaaa84873e3d6020f19e4bfca (diff) | |
| download | qemu-c6f191642a4027909813b4e6e288411f8371e951.tar.gz | |
target-arm: Add AArch64 CPTR registers
Adds CPTR_EL2/3 system registers definitions and access function.
Signed-off-by: Greg Bellows <greg.bellows@linaro.org>
[PMM: merge CPTR_EL2 and HCPTR definitions into a single
def using STATE_BOTH;
don't use readfn/writefn to implement RAZ/WI registers;
don't use accessfn for the no-EL2 CPTR_EL2;
fix cpacr_access logic to catch EL2 accesses to CPACR being
trapped to EL3;
use new CP_ACCESS_TRAP_EL[23] rather than setting
exception.target_el directly]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Diffstat (limited to 'target-arm/cpu.h')
| -rw-r--r-- | target-arm/cpu.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/target-arm/cpu.h b/target-arm/cpu.h index e4313725ac..8cc4bc9fa2 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -197,6 +197,7 @@ typedef struct CPUARMState { uint64_t sctlr_el[4]; }; uint64_t cpacr_el1; /* Architectural feature access control register */ + uint64_t cptr_el[4]; /* ARMv8 feature trap registers */ uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ uint64_t sder; /* Secure debug enable register. */ uint32_t nsacr; /* Non-secure access control register. */ @@ -568,6 +569,10 @@ void pmccntr_sync(CPUARMState *env); #define SCTLR_AFE (1U << 29) #define SCTLR_TE (1U << 30) +#define CPTR_TCPAC (1U << 31) +#define CPTR_TTA (1U << 20) +#define CPTR_TFP (1U << 10) + #define CPSR_M (0x1fU) #define CPSR_T (1U << 5) #define CPSR_F (1U << 6) |