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| author | Peter Maydell <peter.maydell@linaro.org> | 2014-08-19 18:56:25 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2014-08-19 19:02:03 +0100 |
| commit | 48eb3ae64b3e17151cf8f42af185e6f43baf707b (patch) | |
| tree | 99dd56aaba44dbdc92537de9e76c5f07a5946b21 /target-arm/cpu64.c | |
| parent | 10aae1049fe90b84798af2751051ea896437a831 (diff) | |
| download | qemu-48eb3ae64b3e17151cf8f42af185e6f43baf707b.tar.gz | |
target-arm: Adjust debug ID registers per-CPU
Allow each CPU type to specify the value for the debug ID
registers, by putting them in the ARMCPU struct, and use
the resulting information to only expose the correct number
of watchpoint and breakpoint registers for the CPU.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Diffstat (limited to 'target-arm/cpu64.c')
| -rw-r--r-- | target-arm/cpu64.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c index 8b2081c246..38d2b8445a 100644 --- a/target-arm/cpu64.c +++ b/target-arm/cpu64.c @@ -127,6 +127,7 @@ static void aarch64_a57_initfn(Object *obj) cpu->id_aa64dfr0 = 0x10305106; cpu->id_aa64isar0 = 0x00010000; cpu->id_aa64mmfr0 = 0x00001124; + cpu->dbgdidr = 0x3516d000; cpu->clidr = 0x0a200023; cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */ cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */ |