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| author | Edgar E. Iglesias <edgar.iglesias@xilinx.com> | 2015-10-26 14:02:03 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2015-10-27 15:59:47 +0000 |
| commit | e14b5a23d8c83304559f31397f95d22ada60a19a (patch) | |
| tree | a72d80e39e3223ff51c72939cb5f2a7c8b5fed24 /target-arm/internals.h | |
| parent | af51f566ec7106d5e834476e78681a7b354f3c7c (diff) | |
| download | qemu-e14b5a23d8c83304559f31397f95d22ada60a19a.tar.gz | |
target-arm: Add ARMMMUFaultInfo
Introduce ARMMMUFaultInfo to propagate MMU Fault information
across the MMU translation code path. This is in preparation for
adding Stage-2 translation.
No functional changes.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 1445864527-14520-11-git-send-email-edgar.iglesias@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-arm/internals.h')
| -rw-r--r-- | target-arm/internals.h | 15 |
1 files changed, 14 insertions, 1 deletions
diff --git a/target-arm/internals.h b/target-arm/internals.h index 8bd37eba65..412827bcbf 100644 --- a/target-arm/internals.h +++ b/target-arm/internals.h @@ -414,8 +414,21 @@ bool arm_is_psci_call(ARMCPU *cpu, int excp_type); void arm_handle_psci_call(ARMCPU *cpu); #endif +/** + * ARMMMUFaultInfo: Information describing an ARM MMU Fault + * @s2addr: Address that caused a fault at stage 2 + * @stage2: True if we faulted at stage 2 + * @s1ptw: True if we faulted at stage 2 while doing a stage 1 page-table walk + */ +typedef struct ARMMMUFaultInfo ARMMMUFaultInfo; +struct ARMMMUFaultInfo { + target_ulong s2addr; + bool stage2; + bool s1ptw; +}; + /* Do a page table walk and add page to TLB if possible */ bool arm_tlb_fill(CPUState *cpu, vaddr address, int rw, int mmu_idx, - uint32_t *fsr); + uint32_t *fsr, ARMMMUFaultInfo *fi); #endif |