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| author | Peter Maydell <peter.maydell@linaro.org> | 2014-08-19 18:56:26 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2014-08-19 19:02:03 +0100 |
| commit | 4051e12c5df1c46b542b28ed43f1614a42245ecf (patch) | |
| tree | 06aee211a240ff8caa2712de853f62e6c1462c1e /target-arm/op_helper.c | |
| parent | 48eb3ae64b3e17151cf8f42af185e6f43baf707b (diff) | |
| download | qemu-4051e12c5df1c46b542b28ed43f1614a42245ecf.tar.gz | |
target-arm: Don't allow AArch32 to access RES0 CPSR bits
The CPSR has a new-in-v8 execution state bit (IL), and
also some state which has effects in AArch32 but appears
only in the SPSR format (SS) but is RES0 in the CPSR.
Add the IL bit to CPSR_EXEC, and enforce that guest direct
reads and writes to CPSR can't read or write the RES0
bits, so the guest can't get at the SS bit which we store
in uncached_cpsr. This includes not permitting exception
returns to copy reserved bits from an SPSR into CPSR.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Diffstat (limited to 'target-arm/op_helper.c')
| -rw-r--r-- | target-arm/op_helper.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c index 25ad902e04..180a4a096b 100644 --- a/target-arm/op_helper.c +++ b/target-arm/op_helper.c @@ -258,7 +258,7 @@ void HELPER(exception_with_syndrome)(CPUARMState *env, uint32_t excp, uint32_t HELPER(cpsr_read)(CPUARMState *env) { - return cpsr_read(env) & ~CPSR_EXEC; + return cpsr_read(env) & ~(CPSR_EXEC | CPSR_RESERVED); } void HELPER(cpsr_write)(CPUARMState *env, uint32_t val, uint32_t mask) |