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| author | Peter Maydell <peter.maydell@linaro.org> | 2015-05-29 11:28:52 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2015-05-29 11:28:52 +0100 |
| commit | 3cf6a0fcedd429693d439556543400d5f0e31e1d (patch) | |
| tree | 8e8a071f768aaed6cfd35cdc8bd9484ceb1c07f2 /target-arm/translate-a64.c | |
| parent | c6f191642a4027909813b4e6e288411f8371e951 (diff) | |
| download | qemu-3cf6a0fcedd429693d439556543400d5f0e31e1d.tar.gz | |
target-arm: Make singlestate TB flags common between AArch32/64
Currently we keep the TB flags PSTATE_SS and SS_ACTIVE in different
bit positions for AArch64 and AArch32. Replace these separate
definitions with a single common flag in the upper part of the
flags word.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Diffstat (limited to 'target-arm/translate-a64.c')
| -rw-r--r-- | target-arm/translate-a64.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index b1f44c902d..b58778a6b9 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -10975,8 +10975,8 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu, * emit code to generate a software step exception * end the TB */ - dc->ss_active = ARM_TBFLAG_AA64_SS_ACTIVE(tb->flags); - dc->pstate_ss = ARM_TBFLAG_AA64_PSTATE_SS(tb->flags); + dc->ss_active = ARM_TBFLAG_SS_ACTIVE(tb->flags); + dc->pstate_ss = ARM_TBFLAG_PSTATE_SS(tb->flags); dc->is_ldex = false; dc->ss_same_el = (arm_debug_target_el(env) == dc->current_el); |