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| author | Richard Henderson <rth@twiddle.net> | 2015-08-30 09:22:06 -0700 |
|---|---|---|
| committer | Richard Henderson <rth@twiddle.net> | 2015-10-07 20:36:46 +1100 |
| commit | 52e971d9ff67e340ac2a86bd67e14bd31c7991e0 (patch) | |
| tree | fbd3f2e95710bf441a52e308491c9751c1c25162 /target-arm/translate-a64.c | |
| parent | 9aef40ed1f6e2bd794bbb3ba8c8b773e506334c9 (diff) | |
| download | qemu-52e971d9ff67e340ac2a86bd67e14bd31c7991e0.tar.gz | |
target-arm: Add condexec state to insn_start
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target-arm/translate-a64.c')
| -rw-r--r-- | target-arm/translate-a64.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index bc2040e47b..654a58645c 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -11090,7 +11090,7 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu, tcg_ctx.gen_opc_instr_start[lj] = 1; tcg_ctx.gen_opc_icount[lj] = num_insns; } - tcg_gen_insn_start(dc->pc); + tcg_gen_insn_start(dc->pc, 0); num_insns++; if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { |