diff options
| author | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2006-12-06 20:17:30 +0000 |
|---|---|---|
| committer | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2006-12-06 20:17:30 +0000 |
| commit | 7a387fffce508fedae82e3e81b90d1f20c02c783 (patch) | |
| tree | 1291fac9008d87729c2e129b76aa39e79e4b7436 /target-mips/helper.c | |
| parent | 8c0fdd856c63eb11ec5ef955731b1b0cda51f967 (diff) | |
| download | qemu-7a387fffce508fedae82e3e81b90d1f20c02c783.tar.gz | |
Add MIPS32R2 instructions, and generally straighten out the instruction
decoding. This is also the first percent towards MIPS64 support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2224 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-mips/helper.c')
| -rw-r--r-- | target-mips/helper.c | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/target-mips/helper.c b/target-mips/helper.c index 57318a5a34..6b73cb8218 100644 --- a/target-mips/helper.c +++ b/target-mips/helper.c @@ -302,15 +302,9 @@ void do_interrupt (CPUState *env) #endif env->CP0_Wired = 0; env->CP0_Config0 = MIPS_CONFIG0; -#if defined (MIPS_CONFIG1) env->CP0_Config1 = MIPS_CONFIG1; -#endif -#if defined (MIPS_CONFIG2) env->CP0_Config2 = MIPS_CONFIG2; -#endif -#if defined (MIPS_CONFIG3) env->CP0_Config3 = MIPS_CONFIG3; -#endif env->CP0_WatchLo = 0; env->CP0_Status = (1 << CP0St_CU0) | (1 << CP0St_BEV); goto set_error_EPC; |