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| author | Leon Alrae <leon.alrae@imgtec.com> | 2014-07-07 11:23:59 +0100 |
|---|---|---|
| committer | Leon Alrae <leon.alrae@imgtec.com> | 2014-11-03 11:48:34 +0000 |
| commit | 7207c7f9d74816c32783a394d8072d1f978157ac (patch) | |
| tree | 05c22755fc89eceee9d23533de96bc06d9abdd97 /target-mips/translate_init.c | |
| parent | 2fb58b73746e2f99ac85e82160277b18b18279be (diff) | |
| download | qemu-7207c7f9d74816c32783a394d8072d1f978157ac.tar.gz | |
target-mips: update PageGrain and m{t,f}c0 EntryLo{0,1}
PageGrain needs rw bitmask which differs between MIPS architectures.
In pre-R6 if RIXI is supported, PageGrain.XIE and PageGrain.RIE are writeable,
whereas in R6 they are read-only 1.
On MIPS64 mtc0 instruction left shifts bits 31:30 for MIPS32 backward
compatiblity, therefore there are separate mtc0 and dmtc0 helpers.
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
Diffstat (limited to 'target-mips/translate_init.c')
| -rw-r--r-- | target-mips/translate_init.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c index 67b7837750..779afff2d4 100644 --- a/target-mips/translate_init.c +++ b/target-mips/translate_init.c @@ -96,6 +96,8 @@ struct mips_def_t { int32_t CP0_SRSConf3; int32_t CP0_SRSConf4_rw_bitmask; int32_t CP0_SRSConf4; + int32_t CP0_PageGrain_rw_bitmask; + int32_t CP0_PageGrain; int insn_flags; enum mips_mmu_types mmu_type; }; |