diff options
| author | Alex Zuepke <alexander.zuepke@hs-rm.de> | 2014-05-28 19:25:36 +0200 |
|---|---|---|
| committer | Alexander Graf <agraf@suse.de> | 2014-06-16 13:24:40 +0200 |
| commit | a721d390b302a383a99224e08d12caad2e97d7ab (patch) | |
| tree | 8a81b17e463ee4cc8d0c40e89d17716001125c01 /target-ppc/translate_init.c | |
| parent | 1b8eceee280d3fab11812271f4956f7b69287ef0 (diff) | |
| download | qemu-a721d390b302a383a99224e08d12caad2e97d7ab.tar.gz | |
PPC: e500: Fix MMUCSR0 emulation
A "mtspr SPRMMUCSR0, reg" always flushed TLB0,
because it passed the SPR number 0x3f4 to the flush routine.
But we want to flush either TLB0 or TBL1 depending on the GPR value.
Signed-off-by: Alex Zuepke <alexander.zuepke@hs-rm.de>
[agraf: change subject line, fix TCGv size mismatch]
Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'target-ppc/translate_init.c')
| -rw-r--r-- | target-ppc/translate_init.c | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index c13cbba16c..9b342c0438 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -1466,9 +1466,7 @@ static void spr_write_e500_l1csr1(void *opaque, int sprn, int gprn) static void spr_write_booke206_mmucsr0 (void *opaque, int sprn, int gprn) { - TCGv_i32 t0 = tcg_const_i32(sprn); - gen_helper_booke206_tlbflush(cpu_env, t0); - tcg_temp_free_i32(t0); + gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]); } static void spr_write_booke_pid (void *opaque, int sprn, int gprn) |