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| author | Blue Swirl <blauwirbel@gmail.com> | 2012-03-10 20:37:00 +0000 |
|---|---|---|
| committer | Blue Swirl <blauwirbel@gmail.com> | 2012-03-17 16:30:06 +0000 |
| commit | 361dea401f529fc136aaeb49c82b2a5bb7faa316 (patch) | |
| tree | 84fd01e931fbd33f6359e4fe758c087d3f65d551 /target-sparc/cpu.h | |
| parent | 89aaf60dedbe0e6415acfe816e02b538e5c54e68 (diff) | |
| download | qemu-361dea401f529fc136aaeb49c82b2a5bb7faa316.tar.gz | |
sparc64: implement PCI and ISA irqs
Generate correct trap for external interrupts. Map PCI and ISA IRQs to
RIC/UltraSPARC-IIi interrupt vectors.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Diffstat (limited to 'target-sparc/cpu.h')
| -rw-r--r-- | target-sparc/cpu.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h index 887adc3631..f638457a89 100644 --- a/target-sparc/cpu.h +++ b/target-sparc/cpu.h @@ -493,6 +493,9 @@ struct CPUSPARCState { /* UA 2005 hyperprivileged registers */ uint64_t hpstate, htstate[MAXTL_MAX], hintp, htba, hver, hstick_cmpr, ssr; CPUTimer *hstick; // UA 2005 + /* Interrupt vector registers */ + uint64_t ivec_status; + uint64_t ivec_data[3]; uint32_t softint; #define SOFTINT_TIMER 1 #define SOFTINT_STIMER (1 << 16) |