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authorblueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162>2007-09-20 14:54:22 +0000
committerblueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162>2007-09-20 14:54:22 +0000
commit0f8a249a0ba252d7ff61410791712ae9b3449063 (patch)
treeb44cafcd919229e1266d894a3a7eb561aec78817 /target-sparc/translate.c
parent2e03286b9ac5a27c32458a034f51deb3831dac77 (diff)
downloadqemu-0f8a249a0ba252d7ff61410791712ae9b3449063.tar.gz
Detabify
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3195 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-sparc/translate.c')
-rw-r--r--target-sparc/translate.c2932
1 files changed, 1466 insertions, 1466 deletions
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 84f69fcab2..a52d6717a3 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -45,8 +45,8 @@
according to jump_pc[T2] */
typedef struct DisasContext {
- target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC */
- target_ulong npc; /* next PC: integer or DYNAMIC_PC or JUMP_PC */
+ target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC */
+ target_ulong npc; /* next PC: integer or DYNAMIC_PC or JUMP_PC */
target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */
int is_br;
int mem_idx;
@@ -359,57 +359,57 @@ GEN32(gen_op_store_DT1_fpr, gen_op_store_DT1_fpr_fprf);
#define supervisor(dc) 0
#define hypervisor(dc) 0
#define gen_op_ldst(name) gen_op_##name##_raw()
-#define OP_LD_TABLE(width) \
+#define OP_LD_TABLE(width) \
static void gen_op_##width##a(int insn, int is_ld, int size, int sign) \
- { \
- int asi, offset; \
- \
- if (IS_IMM) { \
- offset = GET_FIELD(insn, 25, 31); \
- if (is_ld) \
- gen_op_ld_asi_reg(offset, size, sign); \
- else \
- gen_op_st_asi_reg(offset, size, sign); \
- return; \
- } \
- asi = GET_FIELD(insn, 19, 26); \
- switch (asi) { \
- case 0x80: /* Primary address space */ \
- gen_op_##width##_raw(); \
- break; \
- case 0x82: /* Primary address space, non-faulting load */ \
- gen_op_##width##_raw(); \
- break; \
- default: \
- break; \
- } \
+ { \
+ int asi, offset; \
+ \
+ if (IS_IMM) { \
+ offset = GET_FIELD(insn, 25, 31); \
+ if (is_ld) \
+ gen_op_ld_asi_reg(offset, size, sign); \
+ else \
+ gen_op_st_asi_reg(offset, size, sign); \
+ return; \
+ } \
+ asi = GET_FIELD(insn, 19, 26); \
+ switch (asi) { \
+ case 0x80: /* Primary address space */ \
+ gen_op_##width##_raw(); \
+ break; \
+ case 0x82: /* Primary address space, non-faulting load */ \
+ gen_op_##width##_raw(); \
+ break; \
+ default: \
+ break; \
+ } \
}
#else
#define gen_op_ldst(name) (*gen_op_##name[dc->mem_idx])()
-#define OP_LD_TABLE(width) \
+#define OP_LD_TABLE(width) \
static GenOpFunc * const gen_op_##width[] = { \
- &gen_op_##width##_user, \
- &gen_op_##width##_kernel, \
- }; \
- \
+ &gen_op_##width##_user, \
+ &gen_op_##width##_kernel, \
+ }; \
+ \
static void gen_op_##width##a(int insn, int is_ld, int size, int sign) \
- { \
- int asi, offset; \
- \
- if (IS_IMM) { \
- offset = GET_FIELD(insn, 25, 31); \
- if (is_ld) \
- gen_op_ld_asi_reg(offset, size, sign); \
- else \
- gen_op_st_asi_reg(offset, size, sign); \
- return; \
- } \
- asi = GET_FIELD(insn, 19, 26); \
- if (is_ld) \
- gen_op_ld_asi(asi, size, sign); \
- else \
- gen_op_st_asi(asi, size, sign); \
+ { \
+ int asi, offset; \
+ \
+ if (IS_IMM) { \
+ offset = GET_FIELD(insn, 25, 31); \
+ if (is_ld) \
+ gen_op_ld_asi_reg(offset, size, sign); \
+ else \
+ gen_op_st_asi_reg(offset, size, sign); \
+ return; \
+ } \
+ asi = GET_FIELD(insn, 19, 26); \
+ if (is_ld) \
+ gen_op_ld_asi(asi, size, sign); \
+ else \
+ gen_op_st_asi(asi, size, sign); \
}
#define supervisor(dc) (dc->mem_idx == 1)
@@ -422,7 +422,7 @@ GEN32(gen_op_store_DT1_fpr, gen_op_store_DT1_fpr_fprf);
#define supervisor(dc) 0
#else
#define gen_op_ldst(name) (*gen_op_##name[dc->mem_idx])()
-#define OP_LD_TABLE(width) \
+#define OP_LD_TABLE(width) \
static GenOpFunc * const gen_op_##width[] = { \
&gen_op_##width##_user, \
&gen_op_##width##_kernel, \
@@ -434,23 +434,23 @@ static void gen_op_##width##a(int insn, int is_ld, int size, int sign) \
\
asi = GET_FIELD(insn, 19, 26); \
switch (asi) { \
- case 10: /* User data access */ \
- gen_op_##width##_user(); \
- break; \
- case 11: /* Supervisor data access */ \
- gen_op_##width##_kernel(); \
- break; \
- case 0x20 ... 0x2f: /* MMU passthrough */ \
- if (is_ld) \
- gen_op_ld_asi(asi, size, sign); \
- else \
- gen_op_st_asi(asi, size, sign); \
- break; \
- default: \
- if (is_ld) \
- gen_op_ld_asi(asi, size, sign); \
- else \
- gen_op_st_asi(asi, size, sign); \
+ case 10: /* User data access */ \
+ gen_op_##width##_user(); \
+ break; \
+ case 11: /* Supervisor data access */ \
+ gen_op_##width##_kernel(); \
+ break; \
+ case 0x20 ... 0x2f: /* MMU passthrough */ \
+ if (is_ld) \
+ gen_op_ld_asi(asi, size, sign); \
+ else \
+ gen_op_st_asi(asi, size, sign); \
+ break; \
+ default: \
+ if (is_ld) \
+ gen_op_ld_asi(asi, size, sign); \
+ else \
+ gen_op_st_asi(asi, size, sign); \
break; \
} \
}
@@ -518,9 +518,9 @@ static inline void gen_movl_simm_T0(int32_t val)
static inline void gen_movl_reg_TN(int reg, int t)
{
if (reg)
- gen_op_movl_reg_TN[t][reg] ();
+ gen_op_movl_reg_TN[t][reg] ();
else
- gen_movl_imm_TN(t, 0);
+ gen_movl_imm_TN(t, 0);
}
static inline void gen_movl_reg_T0(int reg)
@@ -541,7 +541,7 @@ static inline void gen_movl_reg_T2(int reg)
static inline void gen_movl_TN_reg(int reg, int t)
{
if (reg)
- gen_op_movl_TN_reg[t][reg] ();
+ gen_op_movl_TN_reg[t][reg] ();
}
static inline void gen_movl_T0_reg(int reg)
@@ -699,118 +699,118 @@ static inline void gen_mov_pc_npc(DisasContext * dc)
static GenOpFunc * const gen_cond[2][16] = {
{
- gen_op_eval_bn,
- gen_op_eval_be,
- gen_op_eval_ble,
- gen_op_eval_bl,
- gen_op_eval_bleu,
- gen_op_eval_bcs,
- gen_op_eval_bneg,
- gen_op_eval_bvs,
- gen_op_eval_ba,
- gen_op_eval_bne,
- gen_op_eval_bg,
- gen_op_eval_bge,
- gen_op_eval_bgu,
- gen_op_eval_bcc,
- gen_op_eval_bpos,
- gen_op_eval_bvc,
+ gen_op_eval_bn,
+ gen_op_eval_be,
+ gen_op_eval_ble,
+ gen_op_eval_bl,
+ gen_op_eval_bleu,
+ gen_op_eval_bcs,
+ gen_op_eval_bneg,
+ gen_op_eval_bvs,
+ gen_op_eval_ba,
+ gen_op_eval_bne,
+ gen_op_eval_bg,
+ gen_op_eval_bge,
+ gen_op_eval_bgu,
+ gen_op_eval_bcc,
+ gen_op_eval_bpos,
+ gen_op_eval_bvc,
},
{
#ifdef TARGET_SPARC64
- gen_op_eval_bn,
- gen_op_eval_xbe,
- gen_op_eval_xble,
- gen_op_eval_xbl,
- gen_op_eval_xbleu,
- gen_op_eval_xbcs,
- gen_op_eval_xbneg,
- gen_op_eval_xbvs,
- gen_op_eval_ba,
- gen_op_eval_xbne,
- gen_op_eval_xbg,
- gen_op_eval_xbge,
- gen_op_eval_xbgu,
- gen_op_eval_xbcc,
- gen_op_eval_xbpos,
- gen_op_eval_xbvc,
+ gen_op_eval_bn,
+ gen_op_eval_xbe,
+ gen_op_eval_xble,
+ gen_op_eval_xbl,
+ gen_op_eval_xbleu,
+ gen_op_eval_xbcs,
+ gen_op_eval_xbneg,
+ gen_op_eval_xbvs,
+ gen_op_eval_ba,
+ gen_op_eval_xbne,
+ gen_op_eval_xbg,
+ gen_op_eval_xbge,
+ gen_op_eval_xbgu,
+ gen_op_eval_xbcc,
+ gen_op_eval_xbpos,
+ gen_op_eval_xbvc,
#endif
},
};
static GenOpFunc * const gen_fcond[4][16] = {
{
- gen_op_eval_bn,
- gen_op_eval_fbne,
- gen_op_eval_fblg,
- gen_op_eval_fbul,
- gen_op_eval_fbl,
- gen_op_eval_fbug,
- gen_op_eval_fbg,
- gen_op_eval_fbu,
- gen_op_eval_ba,
- gen_op_eval_fbe,
- gen_op_eval_fbue,
- gen_op_eval_fbge,
- gen_op_eval_fbuge,
- gen_op_eval_fble,
- gen_op_eval_fbule,
- gen_op_eval_fbo,
+ gen_op_eval_bn,
+ gen_op_eval_fbne,
+ gen_op_eval_fblg,
+ gen_op_eval_fbul,
+ gen_op_eval_fbl,
+ gen_op_eval_fbug,
+ gen_op_eval_fbg,
+ gen_op_eval_fbu,
+ gen_op_eval_ba,
+ gen_op_eval_fbe,
+ gen_op_eval_fbue,
+ gen_op_eval_fbge,
+ gen_op_eval_fbuge,
+ gen_op_eval_fble,
+ gen_op_eval_fbule,
+ gen_op_eval_fbo,
},
#ifdef TARGET_SPARC64
{
- gen_op_eval_bn,
- gen_op_eval_fbne_fcc1,
- gen_op_eval_fblg_fcc1,
- gen_op_eval_fbul_fcc1,
- gen_op_eval_fbl_fcc1,
- gen_op_eval_fbug_fcc1,
- gen_op_eval_fbg_fcc1,
- gen_op_eval_fbu_fcc1,
- gen_op_eval_ba,
- gen_op_eval_fbe_fcc1,
- gen_op_eval_fbue_fcc1,
- gen_op_eval_fbge_fcc1,
- gen_op_eval_fbuge_fcc1,
- gen_op_eval_fble_fcc1,
- gen_op_eval_fbule_fcc1,
- gen_op_eval_fbo_fcc1,
+ gen_op_eval_bn,
+ gen_op_eval_fbne_fcc1,
+ gen_op_eval_fblg_fcc1,
+ gen_op_eval_fbul_fcc1,
+ gen_op_eval_fbl_fcc1,
+ gen_op_eval_fbug_fcc1,
+ gen_op_eval_fbg_fcc1,
+ gen_op_eval_fbu_fcc1,
+ gen_op_eval_ba,
+ gen_op_eval_fbe_fcc1,
+ gen_op_eval_fbue_fcc1,
+ gen_op_eval_fbge_fcc1,
+ gen_op_eval_fbuge_fcc1,
+ gen_op_eval_fble_fcc1,
+ gen_op_eval_fbule_fcc1,
+ gen_op_eval_fbo_fcc1,
},
{
- gen_op_eval_bn,
- gen_op_eval_fbne_fcc2,
- gen_op_eval_fblg_fcc2,
- gen_op_eval_fbul_fcc2,
- gen_op_eval_fbl_fcc2,
- gen_op_eval_fbug_fcc2,
- gen_op_eval_fbg_fcc2,
- gen_op_eval_fbu_fcc2,
- gen_op_eval_ba,
- gen_op_eval_fbe_fcc2,
- gen_op_eval_fbue_fcc2,
- gen_op_eval_fbge_fcc2,
- gen_op_eval_fbuge_fcc2,
- gen_op_eval_fble_fcc2,
- gen_op_eval_fbule_fcc2,
- gen_op_eval_fbo_fcc2,
+ gen_op_eval_bn,
+ gen_op_eval_fbne_fcc2,
+ gen_op_eval_fblg_fcc2,
+ gen_op_eval_fbul_fcc2,
+ gen_op_eval_fbl_fcc2,
+ gen_op_eval_fbug_fcc2,
+ gen_op_eval_fbg_fcc2,
+ gen_op_eval_fbu_fcc2,
+ gen_op_eval_ba,
+ gen_op_eval_fbe_fcc2,
+ gen_op_eval_fbue_fcc2,
+ gen_op_eval_fbge_fcc2,
+ gen_op_eval_fbuge_fcc2,
+ gen_op_eval_fble_fcc2,
+ gen_op_eval_fbule_fcc2,
+ gen_op_eval_fbo_fcc2,
},
{
- gen_op_eval_bn,
- gen_op_eval_fbne_fcc3,
- gen_op_eval_fblg_fcc3,
- gen_op_eval_fbul_fcc3,
- gen_op_eval_fbl_fcc3,
- gen_op_eval_fbug_fcc3,
- gen_op_eval_fbg_fcc3,
- gen_op_eval_fbu_fcc3,
- gen_op_eval_ba,
- gen_op_eval_fbe_fcc3,
- gen_op_eval_fbue_fcc3,
- gen_op_eval_fbge_fcc3,
- gen_op_eval_fbuge_fcc3,
- gen_op_eval_fble_fcc3,
- gen_op_eval_fbule_fcc3,
- gen_op_eval_fbo_fcc3,
+ gen_op_eval_bn,
+ gen_op_eval_fbne_fcc3,
+ gen_op_eval_fblg_fcc3,
+ gen_op_eval_fbul_fcc3,
+ gen_op_eval_fbl_fcc3,
+ gen_op_eval_fbug_fcc3,
+ gen_op_eval_fbg_fcc3,
+ gen_op_eval_fbu_fcc3,
+ gen_op_eval_ba,
+ gen_op_eval_fbe_fcc3,
+ gen_op_eval_fbue_fcc3,
+ gen_op_eval_fbge_fcc3,
+ gen_op_eval_fbuge_fcc3,
+ gen_op_eval_fble_fcc3,
+ gen_op_eval_fbule_fcc3,
+ gen_op_eval_fbo_fcc3,
},
#else
{}, {}, {},
@@ -820,27 +820,27 @@ static GenOpFunc * const gen_fcond[4][16] = {
#ifdef TARGET_SPARC64
static void gen_cond_reg(int cond)
{
- switch (cond) {
- case 0x1:
- gen_op_eval_brz();
- break;
- case 0x2:
- gen_op_eval_brlez();
- break;
- case 0x3:
- gen_op_eval_brlz();
- break;
- case 0x5:
- gen_op_eval_brnz();
- break;
- case 0x6:
- gen_op_eval_brgz();
- break;
+ switch (cond) {
+ case 0x1:
+ gen_op_eval_brz();
+ break;
+ case 0x2:
+ gen_op_eval_brlez();
+ break;
+ case 0x3:
+ gen_op_eval_brlz();
+ break;
+ case 0x5:
+ gen_op_eval_brnz();
+ break;
+ case 0x6:
+ gen_op_eval_brgz();
+ break;
default:
- case 0x7:
- gen_op_eval_brgez();
- break;
- }
+ case 0x7:
+ gen_op_eval_brgez();
+ break;
+ }
}
#endif
@@ -851,35 +851,35 @@ static void do_branch(DisasContext * dc, int32_t offset, uint32_t insn, int cc)
target_ulong target = dc->pc + offset;
if (cond == 0x0) {
- /* unconditional not taken */
- if (a) {
- dc->pc = dc->npc + 4;
- dc->npc = dc->pc + 4;
- } else {
- dc->pc = dc->npc;
- dc->npc = dc->pc + 4;
- }
+ /* unconditional not taken */
+ if (a) {
+ dc->pc = dc->npc + 4;
+ dc->npc = dc->pc + 4;
+ } else {
+ dc->pc = dc->npc;
+ dc->npc = dc->pc + 4;
+ }
} else if (cond == 0x8) {
- /* unconditional taken */
- if (a) {
- dc->pc = target;
- dc->npc = dc->pc + 4;
- } else {
- dc->pc = dc->npc;
- dc->npc = target;
- }
+ /* unconditional taken */
+ if (a) {
+ dc->pc = target;
+ dc->npc = dc->pc + 4;
+ } else {
+ dc->pc = dc->npc;
+ dc->npc = target;
+ }
} else {
flush_T2(dc);
gen_cond[cc][cond]();
- if (a) {
- gen_branch_a(dc, target, dc->npc);
+ if (a) {
+ gen_branch_a(dc, target, dc->npc);
dc->is_br = 1;
- } else {
+ } else {
dc->pc = dc->npc;
dc->jump_pc[0] = target;
dc->jump_pc[1] = dc->npc + 4;
dc->npc = JUMP_PC;
- }
+ }
}
}
@@ -890,35 +890,35 @@ static void do_fbranch(DisasContext * dc, int32_t offset, uint32_t insn, int cc)
target_ulong target = dc->pc + offset;
if (cond == 0x0) {
- /* unconditional not taken */
- if (a) {
- dc->pc = dc->npc + 4;
- dc->npc = dc->pc + 4;
- } else {
- dc->pc = dc->npc;
- dc->npc = dc->pc + 4;
- }
+ /* unconditional not taken */
+ if (a) {
+ dc->pc = dc->npc + 4;
+ dc->npc = dc->pc + 4;
+ } else {
+ dc->pc = dc->npc;
+ dc->npc = dc->pc + 4;
+ }
} else if (cond == 0x8) {
- /* unconditional taken */
- if (a) {
- dc->pc = target;
- dc->npc = dc->pc + 4;
- } else {
- dc->pc = dc->npc;
- dc->npc = target;
- }
+ /* unconditional taken */
+ if (a) {
+ dc->pc = target;
+ dc->npc = dc->pc + 4;
+ } else {
+ dc->pc = dc->npc;
+ dc->npc = target;
+ }
} else {
flush_T2(dc);
gen_fcond[cc][cond]();
- if (a) {
- gen_branch_a(dc, target, dc->npc);
+ if (a) {
+ gen_branch_a(dc, target, dc->npc);
dc->is_br = 1;
- } else {
+ } else {
dc->pc = dc->npc;
dc->jump_pc[0] = target;
dc->jump_pc[1] = dc->npc + 4;
dc->npc = JUMP_PC;
- }
+ }
}
}
@@ -932,13 +932,13 @@ static void do_branch_reg(DisasContext * dc, int32_t offset, uint32_t insn)
flush_T2(dc);
gen_cond_reg(cond);
if (a) {
- gen_branch_a(dc, target, dc->npc);
- dc->is_br = 1;
+ gen_branch_a(dc, target, dc->npc);
+ dc->is_br = 1;
} else {
- dc->pc = dc->npc;
- dc->jump_pc[0] = target;
- dc->jump_pc[1] = dc->npc + 4;
- dc->npc = JUMP_PC;
+ dc->pc = dc->npc;
+ dc->jump_pc[0] = target;
+ dc->jump_pc[1] = dc->npc + 4;
+ dc->npc = JUMP_PC;
}
}
@@ -995,139 +995,139 @@ static void disas_sparc_insn(DisasContext * dc)
rd = GET_FIELD(insn, 2, 6);
switch (opc) {
- case 0: /* branches/sethi */
- {
- unsigned int xop = GET_FIELD(insn, 7, 9);
- int32_t target;
- switch (xop) {
+ case 0: /* branches/sethi */
+ {
+ unsigned int xop = GET_FIELD(insn, 7, 9);
+ int32_t target;
+ switch (xop) {
#ifdef TARGET_SPARC64
- case 0x1: /* V9 BPcc */
- {
- int cc;
-
- target = GET_FIELD_SP(insn, 0, 18);
- target = sign_extend(target, 18);
- target <<= 2;
- cc = GET_FIELD_SP(insn, 20, 21);
- if (cc == 0)
- do_branch(dc, target, insn, 0);
- else if (cc == 2)
- do_branch(dc, target, insn, 1);
- else
- goto illegal_insn;
- goto jmp_insn;
- }
- case 0x3: /* V9 BPr */
- {
- target = GET_FIELD_SP(insn, 0, 13) |
+ case 0x1: /* V9 BPcc */
+ {
+ int cc;
+
+ target = GET_FIELD_SP(insn, 0, 18);
+ target = sign_extend(target, 18);
+ target <<= 2;
+ cc = GET_FIELD_SP(insn, 20, 21);
+ if (cc == 0)
+ do_branch(dc, target, insn, 0);
+ else if (cc == 2)
+ do_branch(dc, target, insn, 1);
+ else
+ goto illegal_insn;
+ goto jmp_insn;
+ }
+ case 0x3: /* V9 BPr */
+ {
+ target = GET_FIELD_SP(insn, 0, 13) |
(GET_FIELD_SP(insn, 20, 21) << 14);
- target = sign_extend(target, 16);
- target <<= 2;
- rs1 = GET_FIELD(insn, 13, 17);
- gen_movl_reg_T0(rs1);
- do_branch_reg(dc, target, insn);
- goto jmp_insn;
- }
- case 0x5: /* V9 FBPcc */
- {
- int cc = GET_FIELD_SP(insn, 20, 21);
+ target = sign_extend(target, 16);
+ target <<= 2;
+ rs1 = GET_FIELD(insn, 13, 17);
+ gen_movl_reg_T0(rs1);
+ do_branch_reg(dc, target, insn);
+ goto jmp_insn;
+ }
+ case 0x5: /* V9 FBPcc */
+ {
+ int cc = GET_FIELD_SP(insn, 20, 21);
if (gen_trap_ifnofpu(dc))
goto jmp_insn;
- target = GET_FIELD_SP(insn, 0, 18);
- target = sign_extend(target, 19);
- target <<= 2;
- do_fbranch(dc, target, insn, cc);
- goto jmp_insn;
- }
+ target = GET_FIELD_SP(insn, 0, 18);
+ target = sign_extend(target, 19);
+ target <<= 2;
+ do_fbranch(dc, target, insn, cc);
+ goto jmp_insn;
+ }
#else
- case 0x7: /* CBN+x */
- {
- goto ncp_insn;
- }
-#endif
- case 0x2: /* BN+x */
- {
- target = GET_FIELD(insn, 10, 31);
- target = sign_extend(target, 22);
- target <<= 2;
- do_branch(dc, target, insn, 0);
- goto jmp_insn;
- }
- case 0x6: /* FBN+x */
- {
+ case 0x7: /* CBN+x */
+ {
+ goto ncp_insn;
+ }
+#endif
+ case 0x2: /* BN+x */
+ {
+ target = GET_FIELD(insn, 10, 31);
+ target = sign_extend(target, 22);
+ target <<= 2;
+ do_branch(dc, target, insn, 0);
+ goto jmp_insn;
+ }
+ case 0x6: /* FBN+x */
+ {
if (gen_trap_ifnofpu(dc))
goto jmp_insn;
- target = GET_FIELD(insn, 10, 31);
- target = sign_extend(target, 22);
- target <<= 2;
- do_fbranch(dc, target, insn, 0);
- goto jmp_insn;
- }
- case 0x4: /* SETHI */
+ target = GET_FIELD(insn, 10, 31);
+ target = sign_extend(target, 22);
+ target <<= 2;
+ do_fbranch(dc, target, insn, 0);
+ goto jmp_insn;
+ }
+ case 0x4: /* SETHI */
#define OPTIM
#if defined(OPTIM)
- if (rd) { // nop
+ if (rd) { // nop
#endif
- uint32_t value = GET_FIELD(insn, 10, 31);
- gen_movl_imm_T0(value << 10);
- gen_movl_T0_reg(rd);
+ uint32_t value = GET_FIELD(insn, 10, 31);
+ gen_movl_imm_T0(value << 10);
+ gen_movl_T0_reg(rd);
#if defined(OPTIM)
- }
+ }
#endif
- break;
- case 0x0: /* UNIMPL */
- default:
+ break;
+ case 0x0: /* UNIMPL */
+ default:
goto illegal_insn;
- }
- break;
- }
- break;
+ }
+ break;
+ }
+ break;
case 1:
- /*CALL*/ {
- target_long target = GET_FIELDs(insn, 2, 31) << 2;
+ /*CALL*/ {
+ target_long target = GET_FIELDs(insn, 2, 31) << 2;
#ifdef TARGET_SPARC64
- if (dc->pc == (uint32_t)dc->pc) {
- gen_op_movl_T0_im(dc->pc);
- } else {
- gen_op_movq_T0_im64(dc->pc >> 32, dc->pc);
- }
+ if (dc->pc == (uint32_t)dc->pc) {
+ gen_op_movl_T0_im(dc->pc);
+ } else {
+ gen_op_movq_T0_im64(dc->pc >> 32, dc->pc);
+ }
#else
- gen_op_movl_T0_im(dc->pc);
+ gen_op_movl_T0_im(dc->pc);
#endif
- gen_movl_T0_reg(15);
- target += dc->pc;
+ gen_movl_T0_reg(15);
+ target += dc->pc;
gen_mov_pc_npc(dc);
- dc->npc = target;
- }
- goto jmp_insn;
- case 2: /* FPU & Logical Operations */
- {
- unsigned int xop = GET_FIELD(insn, 7, 12);
- if (xop == 0x3a) { /* generate trap */
+ dc->npc = target;
+ }
+ goto jmp_insn;
+ case 2: /* FPU & Logical Operations */
+ {
+ unsigned int xop = GET_FIELD(insn, 7, 12);
+ if (xop == 0x3a) { /* generate trap */
int cond;
rs1 = GET_FIELD(insn, 13, 17);
gen_movl_reg_T0(rs1);
- if (IS_IMM) {
- rs2 = GET_FIELD(insn, 25, 31);
+ if (IS_IMM) {
+ rs2 = GET_FIELD(insn, 25, 31);
#if defined(OPTIM)
- if (rs2 != 0) {
+ if (rs2 != 0) {
#endif
- gen_movl_simm_T1(rs2);
- gen_op_add_T1_T0();
+ gen_movl_simm_T1(rs2);
+ gen_op_add_T1_T0();
#if defined(OPTIM)
- }
+ }
#endif
} else {
rs2 = GET_FIELD(insn, 27, 31);
#if defined(OPTIM)
- if (rs2 != 0) {
+ if (rs2 != 0) {
#endif
- gen_movl_reg_T1(rs2);
- gen_op_add_T1_T0();
+ gen_movl_reg_T1(rs2);
+ gen_op_add_T1_T0();
#if defined(OPTIM)
- }
+ }
#endif
}
cond = GET_FIELD(insn, 3, 6);
@@ -1136,20 +1136,20 @@ static void disas_sparc_insn(DisasContext * dc)
gen_op_trap_T0();
} else if (cond != 0) {
#ifdef TARGET_SPARC64
- /* V9 icc/xcc */
- int cc = GET_FIELD_SP(insn, 11, 12);
- flush_T2(dc);
+ /* V9 icc/xcc */
+ int cc = GET_FIELD_SP(insn, 11, 12);
+ flush_T2(dc);
save_state(dc);
- if (cc == 0)
- gen_cond[0][cond]();
- else if (cc == 2)
- gen_cond[1][cond]();
- else
- goto illegal_insn;
+ if (cc == 0)
+ gen_cond[0][cond]();
+ else if (cc == 2)
+ gen_cond[1][cond]();
+ else
+ goto illegal_insn;
#else
- flush_T2(dc);
+ flush_T2(dc);
save_state(dc);
- gen_cond[0][cond]();
+ gen_cond[0][cond]();
#endif
gen_op_trapcc_T0();
}
@@ -1176,56 +1176,56 @@ static void disas_sparc_insn(DisasContext * dc)
gen_movl_T0_reg(rd);
break;
#ifdef TARGET_SPARC64
- case 0x2: /* V9 rdccr */
+ case 0x2: /* V9 rdccr */
gen_op_rdccr();
gen_movl_T0_reg(rd);
break;
- case 0x3: /* V9 rdasi */
- gen_op_movl_T0_env(offsetof(CPUSPARCState, asi));
+ case 0x3: /* V9 rdasi */
+ gen_op_movl_T0_env(offsetof(CPUSPARCState, asi));
gen_movl_T0_reg(rd);
break;
- case 0x4: /* V9 rdtick */
+ case 0x4: /* V9 rdtick */
gen_op_rdtick();
gen_movl_T0_reg(rd);
break;
- case 0x5: /* V9 rdpc */
- if (dc->pc == (uint32_t)dc->pc) {
- gen_op_movl_T0_im(dc->pc);
- } else {
- gen_op_movq_T0_im64(dc->pc >> 32, dc->pc);
- }
- gen_movl_T0_reg(rd);
- break;
- case 0x6: /* V9 rdfprs */
- gen_op_movl_T0_env(offsetof(CPUSPARCState, fprs));
+ case 0x5: /* V9 rdpc */
+ if (dc->pc == (uint32_t)dc->pc) {
+ gen_op_movl_T0_im(dc->pc);
+ } else {
+ gen_op_movq_T0_im64(dc->pc >> 32, dc->pc);
+ }
+ gen_movl_T0_reg(rd);
+ break;
+ case 0x6: /* V9 rdfprs */
+ gen_op_movl_T0_env(offsetof(CPUSPARCState, fprs));
gen_movl_T0_reg(rd);
break;
case 0xf: /* V9 membar */
break; /* no effect */
- case 0x13: /* Graphics Status */
+ case 0x13: /* Graphics Status */
if (gen_trap_ifnofpu(dc))
goto jmp_insn;
- gen_op_movtl_T0_env(offsetof(CPUSPARCState, gsr));
+ gen_op_movtl_T0_env(offsetof(CPUSPARCState, gsr));
gen_movl_T0_reg(rd);
break;
- case 0x17: /* Tick compare */
- gen_op_movtl_T0_env(offsetof(CPUSPARCState, tick_cmpr));
+ case 0x17: /* Tick compare */
+ gen_op_movtl_T0_env(offsetof(CPUSPARCState, tick_cmpr));
gen_movl_T0_reg(rd);
break;
- case 0x18: /* System tick */
+ case 0x18: /* System tick */
gen_op_rdstick();
gen_movl_T0_reg(rd);
break;
- case 0x19: /* System tick compare */
- gen_op_movtl_T0_env(offsetof(CPUSPARCState, stick_cmpr));
+ case 0x19: /* System tick compare */
+ gen_op_movtl_T0_env(offsetof(CPUSPARCState, stick_cmpr));
gen_movl_T0_reg(rd);
break;
- case 0x10: /* Performance Control */
- case 0x11: /* Performance Instrumentation Counter */
- case 0x12: /* Dispatch Control */
- case 0x14: /* Softint set, WO */
- case 0x15: /* Softint clear, WO */
- case 0x16: /* Softint write */
+ case 0x10: /* Performance Control */
+ case 0x11: /* Performance Instrumentation Counter */
+ case 0x12: /* Dispatch Control */
+ case 0x14: /* Softint set, WO */
+ case 0x15: /* Softint clear, WO */
+ case 0x16: /* Softint write */
#endif
default:
goto illegal_insn;
@@ -1233,8 +1233,8 @@ static void disas_sparc_insn(DisasContext * dc)
#if !defined(CONFIG_USER_ONLY)
} else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */
#ifndef TARGET_SPARC64
- if (!supervisor(dc))
- goto priv_insn;
+ if (!supervisor(dc))
+ goto priv_insn;
gen_op_rdpsr();
#else
if (!hypervisor(dc))
@@ -1266,56 +1266,56 @@ static void disas_sparc_insn(DisasContext * dc)
gen_movl_T0_reg(rd);
break;
} else if (xop == 0x2a) { /* rdwim / V9 rdpr */
- if (!supervisor(dc))
- goto priv_insn;
+ if (!supervisor(dc))
+ goto priv_insn;
#ifdef TARGET_SPARC64
rs1 = GET_FIELD(insn, 13, 17);
- switch (rs1) {
- case 0: // tpc
- gen_op_rdtpc();
- break;
- case 1: // tnpc
- gen_op_rdtnpc();
- break;
- case 2: // tstate
- gen_op_rdtstate();
- break;
- case 3: // tt
- gen_op_rdtt();
- break;
- case 4: // tick
- gen_op_rdtick();
- break;
- case 5: // tba
- gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr));
- break;
- case 6: // pstate
- gen_op_rdpstate();
- break;
- case 7: // tl
- gen_op_movl_T0_env(offsetof(CPUSPARCState, tl));
- break;
- case 8: // pil
- gen_op_movl_T0_env(offsetof(CPUSPARCState, psrpil));
- break;
- case 9: // cwp
- gen_op_rdcwp();
- break;
- case 10: // cansave
- gen_op_movl_T0_env(offsetof(CPUSPARCState, cansave));
- break;
- case 11: // canrestore
- gen_op_movl_T0_env(offsetof(CPUSPARCState, canrestore));
- break;
- case 12: // cleanwin
- gen_op_movl_T0_env(offsetof(CPUSPARCState, cleanwin));
- break;
- case 13: // otherwin
- gen_op_movl_T0_env(offsetof(CPUSPARCState, otherwin));
- break;
- case 14: // wstate
- gen_op_movl_T0_env(offsetof(CPUSPARCState, wstate));
- break;
+ switch (rs1) {
+ case 0: // tpc
+ gen_op_rdtpc();
+ break;
+ case 1: // tnpc
+ gen_op_rdtnpc();
+ break;
+ case 2: // tstate
+ gen_op_rdtstate();
+ break;
+ case 3: // tt
+ gen_op_rdtt();
+ break;
+ case 4: // tick
+ gen_op_rdtick();
+ break;
+ case 5: // tba
+ gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr));
+ break;
+ case 6: // pstate
+ gen_op_rdpstate();
+ break;
+ case 7: // tl
+ gen_op_movl_T0_env(offsetof(CPUSPARCState, tl));
+ break;
+ case 8: // pil
+ gen_op_movl_T0_env(offsetof(CPUSPARCState, psrpil));
+ break;
+ case 9: // cwp
+ gen_op_rdcwp();
+ break;
+ case 10: // cansave
+ gen_op_movl_T0_env(offsetof(CPUSPARCState, cansave));
+ break;
+ case 11: // canrestore
+ gen_op_movl_T0_env(offsetof(CPUSPARCState, canrestore));
+ break;
+ case 12: // cleanwin
+ gen_op_movl_T0_env(offsetof(CPUSPARCState, cleanwin));
+ break;
+ case 13: // otherwin
+ gen_op_movl_T0_env(offsetof(CPUSPARCState, otherwin));
+ break;
+ case 14: // wstate
+ gen_op_movl_T0_env(offsetof(CPUSPARCState, wstate));
+ break;
case 16: // UA2005 gl
gen_op_movl_T0_env(offsetof(CPUSPARCState, gl));
break;
@@ -1324,506 +1324,506 @@ static void disas_sparc_insn(DisasContext * dc)
goto priv_insn;
gen_op_movl_T0_env(offsetof(CPUSPARCState, ssr));
break;
- case 31: // ver
- gen_op_movtl_T0_env(offsetof(CPUSPARCState, version));
- break;
- case 15: // fq
- default:
- goto illegal_insn;
- }
+ case 31: // ver
+ gen_op_movtl_T0_env(offsetof(CPUSPARCState, version));
+ break;
+ case 15: // fq
+ default:
+ goto illegal_insn;
+ }
#else
- gen_op_movl_T0_env(offsetof(CPUSPARCState, wim));
+ gen_op_movl_T0_env(offsetof(CPUSPARCState, wim));
#endif
gen_movl_T0_reg(rd);
break;
} else if (xop == 0x2b) { /* rdtbr / V9 flushw */
#ifdef TARGET_SPARC64
- gen_op_flushw();
+ gen_op_flushw();
#else
- if (!supervisor(dc))
- goto priv_insn;
- gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr));
+ if (!supervisor(dc))
+ goto priv_insn;
+ gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr));
gen_movl_T0_reg(rd);
#endif
break;
#endif
- } else if (xop == 0x34) { /* FPU Operations */
+ } else if (xop == 0x34) { /* FPU Operations */
if (gen_trap_ifnofpu(dc))
goto jmp_insn;
- gen_op_clear_ieee_excp_and_FTT();
+ gen_op_clear_ieee_excp_and_FTT();
rs1 = GET_FIELD(insn, 13, 17);
- rs2 = GET_FIELD(insn, 27, 31);
- xop = GET_FIELD(insn, 18, 26);
- switch (xop) {
- case 0x1: /* fmovs */
- gen_op_load_fpr_FT0(rs2);
- gen_op_store_FT0_fpr(rd);
- break;
- case 0x5: /* fnegs */
- gen_op_load_fpr_FT1(rs2);
- gen_op_fnegs();
- gen_op_store_FT0_fpr(rd);
- break;
- case 0x9: /* fabss */
- gen_op_load_fpr_FT1(rs2);
- gen_op_fabss();
- gen_op_store_FT0_fpr(rd);
- break;
- case 0x29: /* fsqrts */
- gen_op_load_fpr_FT1(rs2);
- gen_op_fsqrts();
- gen_op_store_FT0_fpr(rd);
- break;
- case 0x2a: /* fsqrtd */
- gen_op_load_fpr_DT1(DFPREG(rs2));
- gen_op_fsqrtd();
- gen_op_store_DT0_fpr(DFPREG(rd));
- break;
- case 0x2b: /* fsqrtq */
- goto nfpu_insn;
- case 0x41:
- gen_op_load_fpr_FT0(rs1);
- gen_op_load_fpr_FT1(rs2);
- gen_op_fadds();
- gen_op_store_FT0_fpr(rd);
- break;
- case 0x42:
- gen_op_load_fpr_DT0(DFPREG(rs1));
- gen_op_load_fpr_DT1(DFPREG(rs2));
- gen_op_faddd();
- gen_op_store_DT0_fpr(DFPREG(rd));
- break;
- case 0x43: /* faddq */
- goto nfpu_insn;
- case 0x45:
- gen_op_load_fpr_FT0(rs1);
- gen_op_load_fpr_FT1(rs2);
- gen_op_fsubs();
- gen_op_store_FT0_fpr(rd);
- break;
- case 0x46:
- gen_op_load_fpr_DT0(DFPREG(rs1));
- gen_op_load_fpr_DT1(DFPREG(rs2));
- gen_op_fsubd();
- gen_op_store_DT0_fpr(DFPREG(rd));
- break;
- case 0x47: /* fsubq */
- goto nfpu_insn;
- case 0x49:
- gen_op_load_fpr_FT0(rs1);
- gen_op_load_fpr_FT1(rs2);
- gen_op_fmuls();
- gen_op_store_FT0_fpr(rd);
- break;
- case 0x4a:
- gen_op_load_fpr_DT0(DFPREG(rs1));
- gen_op_load_fpr_DT1(DFPREG(rs2));
- gen_op_fmuld();
- gen_op_store_DT0_fpr(rd);
- break;
- case 0x4b: /* fmulq */
- goto nfpu_insn;
- case 0x4d:
- gen_op_load_fpr_FT0(rs1);
- gen_op_load_fpr_FT1(rs2);
- gen_op_fdivs();
- gen_op_store_FT0_fpr(rd);
- break;
- case 0x4e:
- gen_op_load_fpr_DT0(DFPREG(rs1));
- gen_op_load_fpr_DT1(DFPREG(rs2));
- gen_op_fdivd();
- gen_op_store_DT0_fpr(DFPREG(rd));
- break;
- case 0x4f: /* fdivq */
- goto nfpu_insn;
- case 0x69:
- gen_op_load_fpr_FT0(rs1);
- gen_op_load_fpr_FT1(rs2);
- gen_op_fsmuld();
- gen_op_store_DT0_fpr(DFPREG(rd));
- break;
- case 0x6e: /* fdmulq */
- goto nfpu_insn;
- case 0xc4:
- gen_op_load_fpr_FT1(rs2);
- gen_op_fitos();
- gen_op_store_FT0_fpr(rd);
- break;
- case 0xc6:
- gen_op_load_fpr_DT1(DFPREG(rs2));
- gen_op_fdtos();
- gen_op_store_FT0_fpr(rd);
- break;
- case 0xc7: /* fqtos */
- goto nfpu_insn;
- case 0xc8:
- gen_op_load_fpr_FT1(rs2);
- gen_op_fitod();
- gen_op_store_DT0_fpr(DFPREG(rd));
- break;
- case 0xc9:
- gen_op_load_fpr_FT1(rs2);
- gen_op_fstod();
- gen_op_store_DT0_fpr(DFPREG(rd));
- break;
- case 0xcb: /* fqtod */
- goto nfpu_insn;
- case 0xcc: /* fitoq */
- goto nfpu_insn;
- case 0xcd: /* fstoq */
- goto nfpu_insn;
- case 0xce: /* fdtoq */
- goto nfpu_insn;
- case 0xd1:
- gen_op_load_fpr_FT1(rs2);
- gen_op_fstoi();
- gen_op_store_FT0_fpr(rd);
- break;
- case 0xd2:
- gen_op_load_fpr_DT1(rs2);
- gen_op_fdtoi();
- gen_op_store_FT0_fpr(rd);
- break;
- case 0xd3: /* fqtoi */
- goto nfpu_insn;
+ rs2 = GET_FIELD(insn, 27, 31);
+ xop = GET_FIELD(insn, 18, 26);
+ switch (xop) {
+ case 0x1: /* fmovs */
+ gen_op_load_fpr_FT0(rs2);
+ gen_op_store_FT0_fpr(rd);
+ break;
+ case 0x5: /* fnegs */
+ gen_op_load_fpr_FT1(rs2);
+ gen_op_fnegs();
+ gen_op_store_FT0_fpr(rd);
+ break;
+ case 0x9: /* fabss */
+ gen_op_load_fpr_FT1(rs2);
+ gen_op_fabss();
+ gen_op_store_FT0_fpr(rd);
+ break;
+ case 0x29: /* fsqrts */
+ gen_op_load_fpr_FT1(rs2);
+ gen_op_fsqrts();
+ gen_op_store_FT0_fpr(rd);
+ break;
+ case 0x2a: /* fsqrtd */
+ gen_op_load_fpr_DT1(DFPREG(rs2));
+ gen_op_fsqrtd();
+ gen_op_store_DT0_fpr(DFPREG(rd));
+ break;
+ case 0x2b: /* fsqrtq */
+ goto nfpu_insn;
+ case 0x41:
+ gen_op_load_fpr_FT0(rs1);
+ gen_op_load_fpr_FT1(rs2);
+ gen_op_fadds();
+ gen_op_store_FT0_fpr(rd);
+ break;
+ case 0x42:
+ gen_op_load_fpr_DT0(DFPREG(rs1));
+ gen_op_load_fpr_DT1(DFPREG(rs2));
+ gen_op_faddd();
+ gen_op_store_DT0_fpr(DFPREG(rd));
+ break;
+ case 0x43: /* faddq */
+ goto nfpu_insn;
+ case 0x45:
+ gen_op_load_fpr_FT0(rs1);
+ gen_op_load_fpr_FT1(rs2);
+ gen_op_fsubs();
+ gen_op_store_FT0_fpr(rd);
+ break;
+ case 0x46:
+ gen_op_load_fpr_DT0(DFPREG(rs1));
+ gen_op_load_fpr_DT1(DFPREG(rs2));
+ gen_op_fsubd();
+ gen_op_store_DT0_fpr(DFPREG(rd));
+ break;
+ case 0x47: /* fsubq */
+ goto nfpu_insn;
+ case 0x49:
+ gen_op_load_fpr_FT0(rs1);
+ gen_op_load_fpr_FT1(rs2);
+ gen_op_fmuls();
+ gen_op_store_FT0_fpr(rd);
+ break;
+ case 0x4a:
+ gen_op_load_fpr_DT0(DFPREG(rs1));
+ gen_op_load_fpr_DT1(DFPREG(rs2));
+ gen_op_fmuld();
+ gen_op_store_DT0_fpr(rd);
+ break;
+ case 0x4b: /* fmulq */
+ goto nfpu_insn;
+ case 0x4d:
+ gen_op_load_fpr_FT0(rs1);
+ gen_op_load_fpr_FT1(rs2);
+ gen_op_fdivs();
+ gen_op_store_FT0_fpr(rd);
+ break;
+ case 0x4e:
+ gen_op_load_fpr_DT0(DFPREG(rs1));
+ gen_op_load_fpr_DT1(DFPREG(rs2));
+ gen_op_fdivd();
+ gen_op_store_DT0_fpr(DFPREG(rd));
+ break;
+ case 0x4f: /* fdivq */
+ goto nfpu_insn;
+ case 0x69:
+ gen_op_load_fpr_FT0(rs1);
+ gen_op_load_fpr_FT1(rs2);
+ gen_op_fsmuld();
+ gen_op_store_DT0_fpr(DFPREG(rd));
+ break;
+ case 0x6e: /* fdmulq */
+ goto nfpu_insn;
+ case 0xc4:
+ gen_op_load_fpr_FT1(rs2);
+ gen_op_fitos();
+ gen_op_store_FT0_fpr(rd);
+ break;
+ case 0xc6:
+ gen_op_load_fpr_DT1(DFPREG(rs2));
+ gen_op_fdtos();
+ gen_op_store_FT0_fpr(rd);
+ break;
+ case 0xc7: /* fqtos */
+ goto nfpu_insn;
+ case 0xc8:
+ gen_op_load_fpr_FT1(rs2);
+ gen_op_fitod();
+ gen_op_store_DT0_fpr(DFPREG(rd));
+ break;
+ case 0xc9:
+ gen_op_load_fpr_FT1(rs2);
+ gen_op_fstod();
+ gen_op_store_DT0_fpr(DFPREG(rd));
+ break;
+ case 0xcb: /* fqtod */
+ goto nfpu_insn;
+ case 0xcc: /* fitoq */
+ goto nfpu_insn;
+ case 0xcd: /* fstoq */
+ goto nfpu_insn;
+ case 0xce: /* fdtoq */
+ goto nfpu_insn;
+ case 0xd1:
+ gen_op_load_fpr_FT1(rs2);
+ gen_op_fstoi();
+ gen_op_store_FT0_fpr(rd);
+ break;
+ case 0xd2:
+ gen_op_load_fpr_DT1(rs2);
+ gen_op_fdtoi();
+ gen_op_store_FT0_fpr(rd);
+ break;
+ case 0xd3: /* fqtoi */
+ goto nfpu_insn;
#ifdef TARGET_SPARC64
- case 0x2: /* V9 fmovd */
- gen_op_load_fpr_DT0(DFPREG(rs2));
- gen_op_store_DT0_fpr(DFPREG(rd));
- break;
- case 0x6: /* V9 fnegd */
- gen_op_load_fpr_DT1(DFPREG(rs2));
- gen_op_fnegd();
- gen_op_store_DT0_fpr(DFPREG(rd));
- break;
- case 0xa: /* V9 fabsd */
- gen_op_load_fpr_DT1(DFPREG(rs2));
- gen_op_fabsd();
- gen_op_store_DT0_fpr(DFPREG(rd));
- break;
- case 0x81: /* V9 fstox */
- gen_op_load_fpr_FT1(rs2);
- gen_op_fstox();
- gen_op_store_DT0_fpr(DFPREG(rd));
- break;
- case 0x82: /* V9 fdtox */
- gen_op_load_fpr_DT1(DFPREG(rs2));
- gen_op_fdtox();
- gen_op_store_DT0_fpr(DFPREG(rd));
- break;
- case 0x84: /* V9 fxtos */
- gen_op_load_fpr_DT1(DFPREG(rs2));
- gen_op_fxtos();
- gen_op_store_FT0_fpr(rd);
- break;
- case 0x88: /* V9 fxtod */
- gen_op_load_fpr_DT1(DFPREG(rs2));
- gen_op_fxtod();
- gen_op_store_DT0_fpr(DFPREG(rd));
- break;
- case 0x3: /* V9 fmovq */
- case 0x7: /* V9 fnegq */
- case 0xb: /* V9 fabsq */
- case 0x83: /* V9 fqtox */
- case 0x8c: /* V9 fxtoq */
- goto nfpu_insn;
-#endif
- default:
- goto illegal_insn;
- }
- } else if (xop == 0x35) { /* FPU Operations */
+ case 0x2: /* V9 fmovd */
+ gen_op_load_fpr_DT0(DFPREG(rs2));
+ gen_op_store_DT0_fpr(DFPREG(rd));
+ break;
+ case 0x6: /* V9 fnegd */
+ gen_op_load_fpr_DT1(DFPREG(rs2));
+ gen_op_fnegd();
+ gen_op_store_DT0_fpr(DFPREG(rd));
+ break;
+ case 0xa: /* V9 fabsd */
+ gen_op_load_fpr_DT1(DFPREG(rs2));
+ gen_op_fabsd();
+ gen_op_store_DT0_fpr(DFPREG(rd));
+ break;
+ case 0x81: /* V9 fstox */
+ gen_op_load_fpr_FT1(rs2);
+ gen_op_fstox();
+ gen_op_store_DT0_fpr(DFPREG(rd));
+ break;
+ case 0x82: /* V9 fdtox */
+ gen_op_load_fpr_DT1(DFPREG(rs2));
+ gen_op_fdtox();
+ gen_op_store_DT0_fpr(DFPREG(rd));
+ break;
+ case 0x84: /* V9 fxtos */
+ gen_op_load_fpr_DT1(DFPREG(rs2));
+ gen_op_fxtos();
+ gen_op_store_FT0_fpr(rd);
+ break;
+ case 0x88: /* V9 fxtod */
+ gen_op_load_fpr_DT1(DFPREG(rs2));
+ gen_op_fxtod();
+ gen_op_store_DT0_fpr(DFPREG(rd));
+ break;
+ case 0x3: /* V9 fmovq */
+ case 0x7: /* V9 fnegq */
+ case 0xb: /* V9 fabsq */
+ case 0x83: /* V9 fqtox */
+ case 0x8c: /* V9 fxtoq */
+ goto nfpu_insn;
+#endif
+ default:
+ goto illegal_insn;
+ }
+ } else if (xop == 0x35) { /* FPU Operations */
#ifdef TARGET_SPARC64
- int cond;
+ int cond;
#endif
if (gen_trap_ifnofpu(dc))
goto jmp_insn;
- gen_op_clear_ieee_excp_and_FTT();
+ gen_op_clear_ieee_excp_and_FTT();
rs1 = GET_FIELD(insn, 13, 17);
- rs2 = GET_FIELD(insn, 27, 31);
- xop = GET_FIELD(insn, 18, 26);
+ rs2 = GET_FIELD(insn, 27, 31);
+ xop = GET_FIELD(insn, 18, 26);
#ifdef TARGET_SPARC64
- if ((xop & 0x11f) == 0x005) { // V9 fmovsr
- cond = GET_FIELD_SP(insn, 14, 17);
- gen_op_load_fpr_FT0(rd);
- gen_op_load_fpr_FT1(rs2);
- rs1 = GET_FIELD(insn, 13, 17);
- gen_movl_reg_T0(rs1);
- flush_T2(dc);
- gen_cond_reg(cond);
- gen_op_fmovs_cc();
- gen_op_store_FT0_fpr(rd);
- break;
- } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr
- cond = GET_FIELD_SP(insn, 14, 17);
- gen_op_load_fpr_DT0(rd);
- gen_op_load_fpr_DT1(rs2);
- flush_T2(dc);
- rs1 = GET_FIELD(insn, 13, 17);
- gen_movl_reg_T0(rs1);
- gen_cond_reg(cond);
- gen_op_fmovs_cc();
- gen_op_store_DT0_fpr(rd);
- break;
- } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr
- goto nfpu_insn;
- }
-#endif
- switch (xop) {
+ if ((xop & 0x11f) == 0x005) { // V9 fmovsr
+ cond = GET_FIELD_SP(insn, 14, 17);
+ gen_op_load_fpr_FT0(rd);
+ gen_op_load_fpr_FT1(rs2);
+ rs1 = GET_FIELD(insn, 13, 17);
+ gen_movl_reg_T0(rs1);
+ flush_T2(dc);
+ gen_cond_reg(cond);
+ gen_op_fmovs_cc();
+ gen_op_store_FT0_fpr(rd);
+ break;
+ } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr
+ cond = GET_FIELD_SP(insn, 14, 17);
+ gen_op_load_fpr_DT0(rd);
+ gen_op_load_fpr_DT1(rs2);
+ flush_T2(dc);
+ rs1 = GET_FIELD(insn, 13, 17);
+ gen_movl_reg_T0(rs1);
+ gen_cond_reg(cond);
+ gen_op_fmovs_cc();
+ gen_op_store_DT0_fpr(rd);
+ break;
+ } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr
+ goto nfpu_insn;
+ }
+#endif
+ switch (xop) {
#ifdef TARGET_SPARC64
- case 0x001: /* V9 fmovscc %fcc0 */
- cond = GET_FIELD_SP(insn, 14, 17);
- gen_op_load_fpr_FT0(rd);
- gen_op_load_fpr_FT1(rs2);
- flush_T2(dc);
- gen_fcond[0][cond]();
- gen_op_fmovs_cc();
- gen_op_store_FT0_fpr(rd);
- break;
- case 0x002: /* V9 fmovdcc %fcc0 */
- cond = GET_FIELD_SP(insn, 14, 17);
- gen_op_load_fpr_DT0(rd);
- gen_op_load_fpr_DT1(rs2);
- flush_T2(dc);
- gen_fcond[0][cond]();
- gen_op_fmovd_cc();
- gen_op_store_DT0_fpr(rd);
- break;
- case 0x003: /* V9 fmovqcc %fcc0 */
- goto nfpu_insn;
- case 0x041: /* V9 fmovscc %fcc1 */
- cond = GET_FIELD_SP(insn, 14, 17);
- gen_op_load_fpr_FT0(rd);
- gen_op_load_fpr_FT1(rs2);
- flush_T2(dc);
- gen_fcond[1][cond]();
- gen_op_fmovs_cc();
- gen_op_store_FT0_fpr(rd);
- break;
- case 0x042: /* V9 fmovdcc %fcc1 */
- cond = GET_FIELD_SP(insn, 14, 17);
- gen_op_load_fpr_DT0(rd);
- gen_op_load_fpr_DT1(rs2);
- flush_T2(dc);
- gen_fcond[1][cond]();
- gen_op_fmovd_cc();
- gen_op_store_DT0_fpr(rd);
- break;
- case 0x043: /* V9 fmovqcc %fcc1 */
- goto nfpu_insn;
- case 0x081: /* V9 fmovscc %fcc2 */
- cond = GET_FIELD_SP(insn, 14, 17);
- gen_op_load_fpr_FT0(rd);
- gen_op_load_fpr_FT1(rs2);
- flush_T2(dc);
- gen_fcond[2][cond]();
- gen_op_fmovs_cc();
- gen_op_store_FT0_fpr(rd);
- break;
- case 0x082: /* V9 fmovdcc %fcc2 */
- cond = GET_FIELD_SP(insn, 14, 17);
- gen_op_load_fpr_DT0(rd);
- gen_op_load_fpr_DT1(rs2);
- flush_T2(dc);
- gen_fcond[2][cond]();
- gen_op_fmovd_cc();
- gen_op_store_DT0_fpr(rd);
- break;
- case 0x083: /* V9 fmovqcc %fcc2 */
- goto nfpu_insn;
- case 0x0c1: /* V9 fmovscc %fcc3 */
- cond = GET_FIELD_SP(insn, 14, 17);
- gen_op_load_fpr_FT0(rd);
- gen_op_load_fpr_FT1(rs2);
- flush_T2(dc);
- gen_fcond[3][cond]();
- gen_op_fmovs_cc();
- gen_op_store_FT0_fpr(rd);
- break;
- case 0x0c2: /* V9 fmovdcc %fcc3 */
- cond = GET_FIELD_SP(insn, 14, 17);
- gen_op_load_fpr_DT0(rd);
- gen_op_load_fpr_DT1(rs2);
- flush_T2(dc);
- gen_fcond[3][cond]();
- gen_op_fmovd_cc();
- gen_op_store_DT0_fpr(rd);
- break;
- case 0x0c3: /* V9 fmovqcc %fcc3 */
- goto nfpu_insn;
- case 0x101: /* V9 fmovscc %icc */
- cond = GET_FIELD_SP(insn, 14, 17);
- gen_op_load_fpr_FT0(rd);
- gen_op_load_fpr_FT1(rs2);
- flush_T2(dc);
- gen_cond[0][cond]();
- gen_op_fmovs_cc();
- gen_op_store_FT0_fpr(rd);
- break;
- case 0x102: /* V9 fmovdcc %icc */
- cond = GET_FIELD_SP(insn, 14, 17);
- gen_op_load_fpr_DT0(rd);
- gen_op_load_fpr_DT1(rs2);
- flush_T2(dc);
- gen_cond[0][cond]();
- gen_op_fmovd_cc();
- gen_op_store_DT0_fpr(rd);
- break;
- case 0x103: /* V9 fmovqcc %icc */
- goto nfpu_insn;
- case 0x181: /* V9 fmovscc %xcc */
- cond = GET_FIELD_SP(insn, 14, 17);
- gen_op_load_fpr_FT0(rd);
- gen_op_load_fpr_FT1(rs2);
- flush_T2(dc);
- gen_cond[1][cond]();
- gen_op_fmovs_cc();
- gen_op_store_FT0_fpr(rd);
- break;
- case 0x182: /* V9 fmovdcc %xcc */
- cond = GET_FIELD_SP(insn, 14, 17);
- gen_op_load_fpr_DT0(rd);
- gen_op_load_fpr_DT1(rs2);
- flush_T2(dc);
- gen_cond[1][cond]();
- gen_op_fmovd_cc();
- gen_op_store_DT0_fpr(rd);
- break;
- case 0x183: /* V9 fmovqcc %xcc */
- goto nfpu_insn;
-#endif
- case 0x51: /* V9 %fcc */
- gen_op_load_fpr_FT0(rs1);
- gen_op_load_fpr_FT1(rs2);
+ case 0x001: /* V9 fmovscc %fcc0 */
+ cond = GET_FIELD_SP(insn, 14, 17);
+ gen_op_load_fpr_FT0(rd);
+ gen_op_load_fpr_FT1(rs2);
+ flush_T2(dc);
+ gen_fcond[0][cond]();
+ gen_op_fmovs_cc();
+ gen_op_store_FT0_fpr(rd);
+ break;
+ case 0x002: /* V9 fmovdcc %fcc0 */
+ cond = GET_FIELD_SP(insn, 14, 17);
+ gen_op_load_fpr_DT0(rd);
+ gen_op_load_fpr_DT1(rs2);
+ flush_T2(dc);
+ gen_fcond[0][cond]();
+ gen_op_fmovd_cc();
+ gen_op_store_DT0_fpr(rd);
+ break;
+ case 0x003: /* V9 fmovqcc %fcc0 */
+ goto nfpu_insn;
+ case 0x041: /* V9 fmovscc %fcc1 */
+ cond = GET_FIELD_SP(insn, 14, 17);
+ gen_op_load_fpr_FT0(rd);
+ gen_op_load_fpr_FT1(rs2);
+ flush_T2(dc);
+ gen_fcond[1][cond]();
+ gen_op_fmovs_cc();
+ gen_op_store_FT0_fpr(rd);
+ break;
+ case 0x042: /* V9 fmovdcc %fcc1 */
+ cond = GET_FIELD_SP(insn, 14, 17);
+ gen_op_load_fpr_DT0(rd);
+ gen_op_load_fpr_DT1(rs2);
+ flush_T2(dc);
+ gen_fcond[1][cond]();
+ gen_op_fmovd_cc();
+ gen_op_store_DT0_fpr(rd);
+ break;
+ case 0x043: /* V9 fmovqcc %fcc1 */
+ goto nfpu_insn;
+ case 0x081: /* V9 fmovscc %fcc2 */
+ cond = GET_FIELD_SP(insn, 14, 17);
+ gen_op_load_fpr_FT0(rd);
+ gen_op_load_fpr_FT1(rs2);
+ flush_T2(dc);
+ gen_fcond[2][cond]();
+ gen_op_fmovs_cc();
+ gen_op_store_FT0_fpr(rd);
+ break;
+ case 0x082: /* V9 fmovdcc %fcc2 */
+ cond = GET_FIELD_SP(insn, 14, 17);
+ gen_op_load_fpr_DT0(rd);
+ gen_op_load_fpr_DT1(rs2);
+ flush_T2(dc);
+ gen_fcond[2][cond]();
+ gen_op_fmovd_cc();
+ gen_op_store_DT0_fpr(rd);
+ break;
+ case 0x083: /* V9 fmovqcc %fcc2 */
+ goto nfpu_insn;
+ case 0x0c1: /* V9 fmovscc %fcc3 */
+ cond = GET_FIELD_SP(insn, 14, 17);
+ gen_op_load_fpr_FT0(rd);
+ gen_op_load_fpr_FT1(rs2);
+ flush_T2(dc);
+ gen_fcond[3][cond]();
+ gen_op_fmovs_cc();
+ gen_op_store_FT0_fpr(rd);
+ break;
+ case 0x0c2: /* V9 fmovdcc %fcc3 */
+ cond = GET_FIELD_SP(insn, 14, 17);
+ gen_op_load_fpr_DT0(rd);
+ gen_op_load_fpr_DT1(rs2);
+ flush_T2(dc);
+ gen_fcond[3][cond]();
+ gen_op_fmovd_cc();
+ gen_op_store_DT0_fpr(rd);
+ break;
+ case 0x0c3: /* V9 fmovqcc %fcc3 */
+ goto nfpu_insn;
+ case 0x101: /* V9 fmovscc %icc */
+ cond = GET_FIELD_SP(insn, 14, 17);
+ gen_op_load_fpr_FT0(rd);
+ gen_op_load_fpr_FT1(rs2);
+ flush_T2(dc);
+ gen_cond[0][cond]();
+ gen_op_fmovs_cc();
+ gen_op_store_FT0_fpr(rd);
+ break;
+ case 0x102: /* V9 fmovdcc %icc */
+ cond = GET_FIELD_SP(insn, 14, 17);
+ gen_op_load_fpr_DT0(rd);
+ gen_op_load_fpr_DT1(rs2);
+ flush_T2(dc);
+ gen_cond[0][cond]();
+ gen_op_fmovd_cc();
+ gen_op_store_DT0_fpr(rd);
+ break;
+ case 0x103: /* V9 fmovqcc %icc */
+ goto nfpu_insn;
+ case 0x181: /* V9 fmovscc %xcc */
+ cond = GET_FIELD_SP(insn, 14, 17);
+ gen_op_load_fpr_FT0(rd);
+ gen_op_load_fpr_FT1(rs2);
+ flush_T2(dc);
+ gen_cond[1][cond]();
+ gen_op_fmovs_cc();
+ gen_op_store_FT0_fpr(rd);
+ break;
+ case 0x182: /* V9 fmovdcc %xcc */
+ cond = GET_FIELD_SP(insn, 14, 17);
+ gen_op_load_fpr_DT0(rd);
+ gen_op_load_fpr_DT1(rs2);
+ flush_T2(dc);
+ gen_cond[1][cond]();
+ gen_op_fmovd_cc();
+ gen_op_store_DT0_fpr(rd);
+ break;
+ case 0x183: /* V9 fmovqcc %xcc */
+ goto nfpu_insn;
+#endif
+ case 0x51: /* V9 %fcc */
+ gen_op_load_fpr_FT0(rs1);
+ gen_op_load_fpr_FT1(rs2);
#ifdef TARGET_SPARC64
- gen_fcmps[rd & 3]();
+ gen_fcmps[rd & 3]();
#else
- gen_op_fcmps();
+ gen_op_fcmps();
#endif
- break;
- case 0x52: /* V9 %fcc */
- gen_op_load_fpr_DT0(DFPREG(rs1));
- gen_op_load_fpr_DT1(DFPREG(rs2));
+ break;
+ case 0x52: /* V9 %fcc */
+ gen_op_load_fpr_DT0(DFPREG(rs1));
+ gen_op_load_fpr_DT1(DFPREG(rs2));
#ifdef TARGET_SPARC64
- gen_fcmpd[rd & 3]();
+ gen_fcmpd[rd & 3]();
#else
- gen_op_fcmpd();
-#endif
- break;
- case 0x53: /* fcmpq */
- goto nfpu_insn;
- case 0x55: /* fcmpes, V9 %fcc */
- gen_op_load_fpr_FT0(rs1);
- gen_op_load_fpr_FT1(rs2);
+ gen_op_fcmpd();
+#endif
+ break;
+ case 0x53: /* fcmpq */
+ goto nfpu_insn;
+ case 0x55: /* fcmpes, V9 %fcc */
+ gen_op_load_fpr_FT0(rs1);
+ gen_op_load_fpr_FT1(rs2);
#ifdef TARGET_SPARC64
- gen_fcmpes[rd & 3]();
+ gen_fcmpes[rd & 3]();
#else
- gen_op_fcmpes();
+ gen_op_fcmpes();
#endif
- break;
- case 0x56: /* fcmped, V9 %fcc */
- gen_op_load_fpr_DT0(DFPREG(rs1));
- gen_op_load_fpr_DT1(DFPREG(rs2));
+ break;
+ case 0x56: /* fcmped, V9 %fcc */
+ gen_op_load_fpr_DT0(DFPREG(rs1));
+ gen_op_load_fpr_DT1(DFPREG(rs2));
#ifdef TARGET_SPARC64
- gen_fcmped[rd & 3]();
+ gen_fcmped[rd & 3]();
#else
- gen_op_fcmped();
-#endif
- break;
- case 0x57: /* fcmpeq */
- goto nfpu_insn;
- default:
- goto illegal_insn;
- }
+ gen_op_fcmped();
+#endif
+ break;
+ case 0x57: /* fcmpeq */
+ goto nfpu_insn;
+ default:
+ goto illegal_insn;
+ }
#if defined(OPTIM)
- } else if (xop == 0x2) {
- // clr/mov shortcut
+ } else if (xop == 0x2) {
+ // clr/mov shortcut
rs1 = GET_FIELD(insn, 13, 17);
- if (rs1 == 0) {
- // or %g0, x, y -> mov T1, x; mov y, T1
- if (IS_IMM) { /* immediate */
- rs2 = GET_FIELDs(insn, 19, 31);
- gen_movl_simm_T1(rs2);
- } else { /* register */
- rs2 = GET_FIELD(insn, 27, 31);
- gen_movl_reg_T1(rs2);
- }
- gen_movl_T1_reg(rd);
- } else {
- gen_movl_reg_T0(rs1);
- if (IS_IMM) { /* immediate */
- // or x, #0, y -> mov T1, x; mov y, T1
- rs2 = GET_FIELDs(insn, 19, 31);
- if (rs2 != 0) {
- gen_movl_simm_T1(rs2);
- gen_op_or_T1_T0();
- }
- } else { /* register */
- // or x, %g0, y -> mov T1, x; mov y, T1
- rs2 = GET_FIELD(insn, 27, 31);
- if (rs2 != 0) {
- gen_movl_reg_T1(rs2);
- gen_op_or_T1_T0();
- }
- }
- gen_movl_T0_reg(rd);
- }
+ if (rs1 == 0) {
+ // or %g0, x, y -> mov T1, x; mov y, T1
+ if (IS_IMM) { /* immediate */
+ rs2 = GET_FIELDs(insn, 19, 31);
+ gen_movl_simm_T1(rs2);
+ } else { /* register */
+ rs2 = GET_FIELD(insn, 27, 31);
+ gen_movl_reg_T1(rs2);
+ }
+ gen_movl_T1_reg(rd);
+ } else {
+ gen_movl_reg_T0(rs1);
+ if (IS_IMM) { /* immediate */
+ // or x, #0, y -> mov T1, x; mov y, T1
+ rs2 = GET_FIELDs(insn, 19, 31);
+ if (rs2 != 0) {
+ gen_movl_simm_T1(rs2);
+ gen_op_or_T1_T0();
+ }
+ } else { /* register */
+ // or x, %g0, y -> mov T1, x; mov y, T1
+ rs2 = GET_FIELD(insn, 27, 31);
+ if (rs2 != 0) {
+ gen_movl_reg_T1(rs2);
+ gen_op_or_T1_T0();
+ }
+ }
+ gen_movl_T0_reg(rd);
+ }
#endif
#ifdef TARGET_SPARC64
- } else if (xop == 0x25) { /* sll, V9 sllx */
+ } else if (xop == 0x25) { /* sll, V9 sllx */
rs1 = GET_FIELD(insn, 13, 17);
- gen_movl_reg_T0(rs1);
- if (IS_IMM) { /* immediate */
+ gen_movl_reg_T0(rs1);
+ if (IS_IMM) { /* immediate */
rs2 = GET_FIELDs(insn, 20, 31);
gen_movl_simm_T1(rs2);
- } else { /* register */
+ } else { /* register */
rs2 = GET_FIELD(insn, 27, 31);
gen_movl_reg_T1(rs2);
}
- if (insn & (1 << 12))
- gen_op_sllx();
- else
- gen_op_sll();
- gen_movl_T0_reg(rd);
- } else if (xop == 0x26) { /* srl, V9 srlx */
+ if (insn & (1 << 12))
+ gen_op_sllx();
+ else
+ gen_op_sll();
+ gen_movl_T0_reg(rd);
+ } else if (xop == 0x26) { /* srl, V9 srlx */
rs1 = GET_FIELD(insn, 13, 17);
- gen_movl_reg_T0(rs1);
- if (IS_IMM) { /* immediate */
+ gen_movl_reg_T0(rs1);
+ if (IS_IMM) { /* immediate */
rs2 = GET_FIELDs(insn, 20, 31);
gen_movl_simm_T1(rs2);
- } else { /* register */
+ } else { /* register */
rs2 = GET_FIELD(insn, 27, 31);
gen_movl_reg_T1(rs2);
}
- if (insn & (1 << 12))
- gen_op_srlx();
- else
- gen_op_srl();
- gen_movl_T0_reg(rd);
- } else if (xop == 0x27) { /* sra, V9 srax */
+ if (insn & (1 << 12))
+ gen_op_srlx();
+ else
+ gen_op_srl();
+ gen_movl_T0_reg(rd);
+ } else if (xop == 0x27) { /* sra, V9 srax */
rs1 = GET_FIELD(insn, 13, 17);
- gen_movl_reg_T0(rs1);
- if (IS_IMM) { /* immediate */
+ gen_movl_reg_T0(rs1);
+ if (IS_IMM) { /* immediate */
rs2 = GET_FIELDs(insn, 20, 31);
gen_movl_simm_T1(rs2);
- } else { /* register */
+ } else { /* register */
rs2 = GET_FIELD(insn, 27, 31);
gen_movl_reg_T1(rs2);
}
- if (insn & (1 << 12))
- gen_op_srax();
- else
- gen_op_sra();
- gen_movl_T0_reg(rd);
+ if (insn & (1 << 12))
+ gen_op_srax();
+ else
+ gen_op_sra();
+ gen_movl_T0_reg(rd);
#endif
} else if (xop < 0x36) {
rs1 = GET_FIELD(insn, 13, 17);
- gen_movl_reg_T0(rs1);
- if (IS_IMM) { /* immediate */
+ gen_movl_reg_T0(rs1);
+ if (IS_IMM) { /* immediate */
rs2 = GET_FIELDs(insn, 19, 31);
gen_movl_simm_T1(rs2);
- } else { /* register */
+ } else { /* register */
rs2 = GET_FIELD(insn, 27, 31);
gen_movl_reg_T1(rs2);
}
@@ -1841,10 +1841,10 @@ static void disas_sparc_insn(DisasContext * dc)
gen_op_logic_T0_cc();
break;
case 0x2:
- gen_op_or_T1_T0();
- if (xop & 0x10)
- gen_op_logic_T0_cc();
- break;
+ gen_op_or_T1_T0();
+ if (xop & 0x10)
+ gen_op_logic_T0_cc();
+ break;
case 0x3:
gen_op_xor_T1_T0();
if (xop & 0x10)
@@ -1878,7 +1878,7 @@ static void disas_sparc_insn(DisasContext * dc)
gen_op_addx_T1_T0();
break;
#ifdef TARGET_SPARC64
- case 0x9: /* V9 mulx */
+ case 0x9: /* V9 mulx */
gen_op_mulx_T1_T0();
break;
#endif
@@ -1899,7 +1899,7 @@ static void disas_sparc_insn(DisasContext * dc)
gen_op_subx_T1_T0();
break;
#ifdef TARGET_SPARC64
- case 0xd: /* V9 udivx */
+ case 0xd: /* V9 udivx */
gen_op_udivx_T1_T0();
break;
#endif
@@ -1916,40 +1916,40 @@ static void disas_sparc_insn(DisasContext * dc)
default:
goto illegal_insn;
}
- gen_movl_T0_reg(rd);
+ gen_movl_T0_reg(rd);
} else {
switch (xop) {
- case 0x20: /* taddcc */
- gen_op_tadd_T1_T0_cc();
- gen_movl_T0_reg(rd);
- break;
- case 0x21: /* tsubcc */
- gen_op_tsub_T1_T0_cc();
- gen_movl_T0_reg(rd);
- break;
- case 0x22: /* taddcctv */
- gen_op_tadd_T1_T0_ccTV();
- gen_movl_T0_reg(rd);
- break;
- case 0x23: /* tsubcctv */
- gen_op_tsub_T1_T0_ccTV();
- gen_movl_T0_reg(rd);
- break;
+ case 0x20: /* taddcc */
+ gen_op_tadd_T1_T0_cc();
+ gen_movl_T0_reg(rd);
+ break;
+ case 0x21: /* tsubcc */
+ gen_op_tsub_T1_T0_cc();
+ gen_movl_T0_reg(rd);
+ break;
+ case 0x22: /* taddcctv */
+ gen_op_tadd_T1_T0_ccTV();
+ gen_movl_T0_reg(rd);
+ break;
+ case 0x23: /* tsubcctv */
+ gen_op_tsub_T1_T0_ccTV();
+ gen_movl_T0_reg(rd);
+ break;
case 0x24: /* mulscc */
gen_op_mulscc_T1_T0();
gen_movl_T0_reg(rd);
break;
#ifndef TARGET_SPARC64
- case 0x25: /* sll */
- gen_op_sll();
+ case 0x25: /* sll */
+ gen_op_sll();
gen_movl_T0_reg(rd);
break;
case 0x26: /* srl */
- gen_op_srl();
+ gen_op_srl();
gen_movl_T0_reg(rd);
break;
case 0x27: /* sra */
- gen_op_sra();
+ gen_op_sra();
gen_movl_T0_reg(rd);
break;
#endif
@@ -1957,8 +1957,8 @@ static void disas_sparc_insn(DisasContext * dc)
{
switch(rd) {
case 0: /* wry */
- gen_op_xor_T1_T0();
- gen_op_movtl_env_T0(offsetof(CPUSPARCState, y));
+ gen_op_xor_T1_T0();
+ gen_op_movtl_env_T0(offsetof(CPUSPARCState, y));
break;
#ifndef TARGET_SPARC64
case 0x01 ... 0x0f: /* undefined in the
@@ -1971,62 +1971,62 @@ static void disas_sparc_insn(DisasContext * dc)
microSPARC II */
break;
#else
- case 0x2: /* V9 wrccr */
+ case 0x2: /* V9 wrccr */
gen_op_wrccr();
- break;
- case 0x3: /* V9 wrasi */
- gen_op_movl_env_T0(offsetof(CPUSPARCState, asi));
- break;
- case 0x6: /* V9 wrfprs */
- gen_op_xor_T1_T0();
- gen_op_movl_env_T0(offsetof(CPUSPARCState, fprs));
+ break;
+ case 0x3: /* V9 wrasi */
+ gen_op_movl_env_T0(offsetof(CPUSPARCState, asi));
+ break;
+ case 0x6: /* V9 wrfprs */
+ gen_op_xor_T1_T0();
+ gen_op_movl_env_T0(offsetof(CPUSPARCState, fprs));
save_state(dc);
gen_op_next_insn();
gen_op_movl_T0_0();
gen_op_exit_tb();
dc->is_br = 1;
- break;
- case 0xf: /* V9 sir, nop if user */
+ break;
+ case 0xf: /* V9 sir, nop if user */
#if !defined(CONFIG_USER_ONLY)
- if (supervisor(dc))
- gen_op_sir();
+ if (supervisor(dc))
+ gen_op_sir();
#endif
- break;
- case 0x13: /* Graphics Status */
+ break;
+ case 0x13: /* Graphics Status */
if (gen_trap_ifnofpu(dc))
goto jmp_insn;
- gen_op_movtl_env_T0(offsetof(CPUSPARCState, gsr));
- break;
- case 0x17: /* Tick compare */
+ gen_op_movtl_env_T0(offsetof(CPUSPARCState, gsr));
+ break;
+ case 0x17: /* Tick compare */
#if !defined(CONFIG_USER_ONLY)
- if (!supervisor(dc))
- goto illegal_insn;
+ if (!supervisor(dc))
+ goto illegal_insn;
#endif
gen_op_movtl_env_T0(offsetof(CPUSPARCState, tick_cmpr));
gen_op_wrtick_cmpr();
- break;
- case 0x18: /* System tick */
+ break;
+ case 0x18: /* System tick */
#if !defined(CONFIG_USER_ONLY)
- if (!supervisor(dc))
- goto illegal_insn;
+ if (!supervisor(dc))
+ goto illegal_insn;
#endif
gen_op_wrstick();
- break;
- case 0x19: /* System tick compare */
+ break;
+ case 0x19: /* System tick compare */
#if !defined(CONFIG_USER_ONLY)
- if (!supervisor(dc))
- goto illegal_insn;
+ if (!supervisor(dc))
+ goto illegal_insn;
#endif
gen_op_movtl_env_T0(offsetof(CPUSPARCState, stick_cmpr));
gen_op_wrstick_cmpr();
- break;
+ break;
- case 0x10: /* Performance Control */
- case 0x11: /* Performance Instrumentation Counter */
- case 0x12: /* Dispatch Control */
- case 0x14: /* Softint set */
- case 0x15: /* Softint clear */
- case 0x16: /* Softint write */
+ case 0x10: /* Performance Control */
+ case 0x11: /* Performance Instrumentation Counter */
+ case 0x12: /* Dispatch Control */
+ case 0x14: /* Softint set */
+ case 0x15: /* Softint clear */
+ case 0x16: /* Softint write */
#endif
default:
goto illegal_insn;
@@ -2036,22 +2036,22 @@ static void disas_sparc_insn(DisasContext * dc)
#if !defined(CONFIG_USER_ONLY)
case 0x31: /* wrpsr, V9 saved, restored */
{
- if (!supervisor(dc))
- goto priv_insn;
+ if (!supervisor(dc))
+ goto priv_insn;
#ifdef TARGET_SPARC64
- switch (rd) {
- case 0:
- gen_op_saved();
- break;
- case 1:
- gen_op_restored();
- break;
+ switch (rd) {
+ case 0:
+ gen_op_saved();
+ break;
+ case 1:
+ gen_op_restored();
+ break;
case 2: /* UA2005 allclean */
case 3: /* UA2005 otherw */
case 4: /* UA2005 normalw */
case 5: /* UA2005 invalw */
// XXX
- default:
+ default:
goto illegal_insn;
}
#else
@@ -2059,69 +2059,69 @@ static void disas_sparc_insn(DisasContext * dc)
gen_op_wrpsr();
save_state(dc);
gen_op_next_insn();
- gen_op_movl_T0_0();
- gen_op_exit_tb();
- dc->is_br = 1;
+ gen_op_movl_T0_0();
+ gen_op_exit_tb();
+ dc->is_br = 1;
#endif
}
break;
case 0x32: /* wrwim, V9 wrpr */
{
- if (!supervisor(dc))
- goto priv_insn;
+ if (!supervisor(dc))
+ goto priv_insn;
gen_op_xor_T1_T0();
#ifdef TARGET_SPARC64
- switch (rd) {
- case 0: // tpc
- gen_op_wrtpc();
- break;
- case 1: // tnpc
- gen_op_wrtnpc();
- break;
- case 2: // tstate
- gen_op_wrtstate();
- break;
- case 3: // tt
- gen_op_wrtt();
- break;
- case 4: // tick
- gen_op_wrtick();
- break;
- case 5: // tba
- gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr));
- break;
- case 6: // pstate
- gen_op_wrpstate();
+ switch (rd) {
+ case 0: // tpc
+ gen_op_wrtpc();
+ break;
+ case 1: // tnpc
+ gen_op_wrtnpc();
+ break;
+ case 2: // tstate
+ gen_op_wrtstate();
+ break;
+ case 3: // tt
+ gen_op_wrtt();
+ break;
+ case 4: // tick
+ gen_op_wrtick();
+ break;
+ case 5: // tba
+ gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr));
+ break;
+ case 6: // pstate
+ gen_op_wrpstate();
save_state(dc);
gen_op_next_insn();
gen_op_movl_T0_0();
gen_op_exit_tb();
dc->is_br = 1;
- break;
- case 7: // tl
- gen_op_movl_env_T0(offsetof(CPUSPARCState, tl));
- break;
- case 8: // pil
- gen_op_movl_env_T0(offsetof(CPUSPARCState, psrpil));
- break;
- case 9: // cwp
- gen_op_wrcwp();
- break;
- case 10: // cansave
- gen_op_movl_env_T0(offsetof(CPUSPARCState, cansave));
- break;
- case 11: // canrestore
- gen_op_movl_env_T0(offsetof(CPUSPARCState, canrestore));
- break;
- case 12: // cleanwin
- gen_op_movl_env_T0(offsetof(CPUSPARCState, cleanwin));
- break;
- case 13: // otherwin
- gen_op_movl_env_T0(offsetof(CPUSPARCState, otherwin));
- break;
- case 14: // wstate
- gen_op_movl_env_T0(offsetof(CPUSPARCState, wstate));
- break;
+ break;
+ case 7: // tl
+ gen_op_movl_env_T0(offsetof(CPUSPARCState, tl));
+ break;
+ case 8: // pil
+ gen_op_movl_env_T0(offsetof(CPUSPARCState, psrpil));
+ break;
+ case 9: // cwp
+ gen_op_wrcwp();
+ break;
+ case 10: // cansave
+ gen_op_movl_env_T0(offsetof(CPUSPARCState, cansave));
+ break;
+ case 11: // canrestore
+ gen_op_movl_env_T0(offsetof(CPUSPARCState, canrestore));
+ break;
+ case 12: // cleanwin
+ gen_op_movl_env_T0(offsetof(CPUSPARCState, cleanwin));
+ break;
+ case 13: // otherwin
+ gen_op_movl_env_T0(offsetof(CPUSPARCState, otherwin));
+ break;
+ case 14: // wstate
+ gen_op_movl_env_T0(offsetof(CPUSPARCState, wstate));
+ break;
case 16: // UA2005 gl
gen_op_movl_env_T0(offsetof(CPUSPARCState, gl));
break;
@@ -2130,19 +2130,19 @@ static void disas_sparc_insn(DisasContext * dc)
goto priv_insn;
gen_op_movl_env_T0(offsetof(CPUSPARCState, ssr));
break;
- default:
- goto illegal_insn;
- }
+ default:
+ goto illegal_insn;
+ }
#else
- gen_op_wrwim();
+ gen_op_wrwim();
#endif
}
break;
case 0x33: /* wrtbr, UA2005 wrhpr */
{
#ifndef TARGET_SPARC64
- if (!supervisor(dc))
- goto priv_insn;
+ if (!supervisor(dc))
+ goto priv_insn;
gen_op_xor_T1_T0();
gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr));
#else
@@ -2180,77 +2180,77 @@ static void disas_sparc_insn(DisasContext * dc)
break;
#endif
#ifdef TARGET_SPARC64
- case 0x2c: /* V9 movcc */
- {
- int cc = GET_FIELD_SP(insn, 11, 12);
- int cond = GET_FIELD_SP(insn, 14, 17);
- if (IS_IMM) { /* immediate */
- rs2 = GET_FIELD_SPs(insn, 0, 10);
- gen_movl_simm_T1(rs2);
- }
- else {
- rs2 = GET_FIELD_SP(insn, 0, 4);
- gen_movl_reg_T1(rs2);
- }
- gen_movl_reg_T0(rd);
- flush_T2(dc);
- if (insn & (1 << 18)) {
- if (cc == 0)
- gen_cond[0][cond]();
- else if (cc == 2)
- gen_cond[1][cond]();
- else
- goto illegal_insn;
- } else {
- gen_fcond[cc][cond]();
- }
- gen_op_mov_cc();
- gen_movl_T0_reg(rd);
- break;
- }
- case 0x2d: /* V9 sdivx */
+ case 0x2c: /* V9 movcc */
+ {
+ int cc = GET_FIELD_SP(insn, 11, 12);
+ int cond = GET_FIELD_SP(insn, 14, 17);
+ if (IS_IMM) { /* immediate */
+ rs2 = GET_FIELD_SPs(insn, 0, 10);
+ gen_movl_simm_T1(rs2);
+ }
+ else {
+ rs2 = GET_FIELD_SP(insn, 0, 4);
+ gen_movl_reg_T1(rs2);
+ }
+ gen_movl_reg_T0(rd);
+ flush_T2(dc);
+ if (insn & (1 << 18)) {
+ if (cc == 0)
+ gen_cond[0][cond]();
+ else if (cc == 2)
+ gen_cond[1][cond]();
+ else
+ goto illegal_insn;
+ } else {
+ gen_fcond[cc][cond]();
+ }
+ gen_op_mov_cc();
+ gen_movl_T0_reg(rd);
+ break;
+ }
+ case 0x2d: /* V9 sdivx */
gen_op_sdivx_T1_T0();
- gen_movl_T0_reg(rd);
- break;
- case 0x2e: /* V9 popc */
- {
- if (IS_IMM) { /* immediate */
- rs2 = GET_FIELD_SPs(insn, 0, 12);
- gen_movl_simm_T1(rs2);
- // XXX optimize: popc(constant)
- }
- else {
- rs2 = GET_FIELD_SP(insn, 0, 4);
- gen_movl_reg_T1(rs2);
- }
- gen_op_popc();
- gen_movl_T0_reg(rd);
- }
- case 0x2f: /* V9 movr */
- {
- int cond = GET_FIELD_SP(insn, 10, 12);
- rs1 = GET_FIELD(insn, 13, 17);
- flush_T2(dc);
- gen_movl_reg_T0(rs1);
- gen_cond_reg(cond);
- if (IS_IMM) { /* immediate */
- rs2 = GET_FIELD_SPs(insn, 0, 9);
- gen_movl_simm_T1(rs2);
- }
- else {
- rs2 = GET_FIELD_SP(insn, 0, 4);
- gen_movl_reg_T1(rs2);
- }
- gen_movl_reg_T0(rd);
- gen_op_mov_cc();
- gen_movl_T0_reg(rd);
- break;
- }
-#endif
- default:
- goto illegal_insn;
- }
- }
+ gen_movl_T0_reg(rd);
+ break;
+ case 0x2e: /* V9 popc */
+ {
+ if (IS_IMM) { /* immediate */
+ rs2 = GET_FIELD_SPs(insn, 0, 12);
+ gen_movl_simm_T1(rs2);
+ // XXX optimize: popc(constant)
+ }
+ else {
+ rs2 = GET_FIELD_SP(insn, 0, 4);
+ gen_movl_reg_T1(rs2);
+ }
+ gen_op_popc();
+ gen_movl_T0_reg(rd);
+ }
+ case 0x2f: /* V9 movr */
+ {
+ int cond = GET_FIELD_SP(insn, 10, 12);
+ rs1 = GET_FIELD(insn, 13, 17);
+ flush_T2(dc);
+ gen_movl_reg_T0(rs1);
+ gen_cond_reg(cond);
+ if (IS_IMM) { /* immediate */
+ rs2 = GET_FIELD_SPs(insn, 0, 9);
+ gen_movl_simm_T1(rs2);
+ }
+ else {
+ rs2 = GET_FIELD_SP(insn, 0, 4);
+ gen_movl_reg_T1(rs2);
+ }
+ gen_movl_reg_T0(rd);
+ gen_op_mov_cc();
+ gen_movl_T0_reg(rd);
+ break;
+ }
+#endif
+ default:
+ goto illegal_insn;
+ }
+ }
} else if (xop == 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */
#ifdef TARGET_SPARC64
int opf = GET_FIELD_SP(insn, 5, 13);
@@ -2647,75 +2647,75 @@ static void disas_sparc_insn(DisasContext * dc)
goto illegal_insn;
}
#else
- goto ncp_insn;
+ goto ncp_insn;
#endif
} else if (xop == 0x37) { /* V8 CPop2, V9 impdep2 */
#ifdef TARGET_SPARC64
- goto illegal_insn;
+ goto illegal_insn;
#else
- goto ncp_insn;
+ goto ncp_insn;
#endif
#ifdef TARGET_SPARC64
- } else if (xop == 0x39) { /* V9 return */
+ } else if (xop == 0x39) { /* V9 return */
rs1 = GET_FIELD(insn, 13, 17);
save_state(dc);
- gen_movl_reg_T0(rs1);
- if (IS_IMM) { /* immediate */
- rs2 = GET_FIELDs(insn, 19, 31);
+ gen_movl_reg_T0(rs1);
+ if (IS_IMM) { /* immediate */
+ rs2 = GET_FIELDs(insn, 19, 31);
#if defined(OPTIM)
- if (rs2) {
+ if (rs2) {
#endif
- gen_movl_simm_T1(rs2);
- gen_op_add_T1_T0();
+ gen_movl_simm_T1(rs2);
+ gen_op_add_T1_T0();
#if defined(OPTIM)
- }
+ }
#endif
- } else { /* register */
+ } else { /* register */
rs2 = GET_FIELD(insn, 27, 31);
#if defined(OPTIM)
- if (rs2) {
+ if (rs2) {
#endif
- gen_movl_reg_T1(rs2);
- gen_op_add_T1_T0();
+ gen_movl_reg_T1(rs2);
+ gen_op_add_T1_T0();
#if defined(OPTIM)
- }
+ }
#endif
}
- gen_op_restore();
- gen_mov_pc_npc(dc);
+ gen_op_restore();
+ gen_mov_pc_npc(dc);
gen_op_check_align_T0_3();
- gen_op_movl_npc_T0();
- dc->npc = DYNAMIC_PC;
- goto jmp_insn;
+ gen_op_movl_npc_T0();
+ dc->npc = DYNAMIC_PC;
+ goto jmp_insn;
#endif
- } else {
+ } else {
rs1 = GET_FIELD(insn, 13, 17);
- gen_movl_reg_T0(rs1);
- if (IS_IMM) { /* immediate */
- rs2 = GET_FIELDs(insn, 19, 31);
+ gen_movl_reg_T0(rs1);
+ if (IS_IMM) { /* immediate */
+ rs2 = GET_FIELDs(insn, 19, 31);
#if defined(OPTIM)
- if (rs2) {
+ if (rs2) {
#endif
- gen_movl_simm_T1(rs2);
- gen_op_add_T1_T0();
+ gen_movl_simm_T1(rs2);
+ gen_op_add_T1_T0();
#if defined(OPTIM)
- }
+ }
#endif
- } else { /* register */
+ } else { /* register */
rs2 = GET_FIELD(insn, 27, 31);
#if defined(OPTIM)
- if (rs2) {
+ if (rs2) {
#endif
- gen_movl_reg_T1(rs2);
- gen_op_add_T1_T0();
+ gen_movl_reg_T1(rs2);
+ gen_op_add_T1_T0();
#if defined(OPTIM)
- }
+ }
#endif
}
- switch (xop) {
- case 0x38: /* jmpl */
- {
- if (rd != 0) {
+ switch (xop) {
+ case 0x38: /* jmpl */
+ {
+ if (rd != 0) {
#ifdef TARGET_SPARC64
if (dc->pc == (uint32_t)dc->pc) {
gen_op_movl_T1_im(dc->pc);
@@ -2723,250 +2723,250 @@ static void disas_sparc_insn(DisasContext * dc)
gen_op_movq_T1_im64(dc->pc >> 32, dc->pc);
}
#else
- gen_op_movl_T1_im(dc->pc);
+ gen_op_movl_T1_im(dc->pc);
#endif
- gen_movl_T1_reg(rd);
- }
+ gen_movl_T1_reg(rd);
+ }
gen_mov_pc_npc(dc);
gen_op_check_align_T0_3();
- gen_op_movl_npc_T0();
- dc->npc = DYNAMIC_PC;
- }
- goto jmp_insn;
+ gen_op_movl_npc_T0();
+ dc->npc = DYNAMIC_PC;
+ }
+ goto jmp_insn;
#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
- case 0x39: /* rett, V9 return */
- {
- if (!supervisor(dc))
- goto priv_insn;
+ case 0x39: /* rett, V9 return */
+ {
+ if (!supervisor(dc))
+ goto priv_insn;
gen_mov_pc_npc(dc);
gen_op_check_align_T0_3();
- gen_op_movl_npc_T0();
- dc->npc = DYNAMIC_PC;
- gen_op_rett();
- }
- goto jmp_insn;
-#endif
- case 0x3b: /* flush */
- gen_op_flush_T0();
- break;
- case 0x3c: /* save */
- save_state(dc);
- gen_op_save();
- gen_movl_T0_reg(rd);
- break;
- case 0x3d: /* restore */
- save_state(dc);
- gen_op_restore();
- gen_movl_T0_reg(rd);
- break;
+ gen_op_movl_npc_T0();
+ dc->npc = DYNAMIC_PC;
+ gen_op_rett();
+ }
+ goto jmp_insn;
+#endif
+ case 0x3b: /* flush */
+ gen_op_flush_T0();
+ break;
+ case 0x3c: /* save */
+ save_state(dc);
+ gen_op_save();
+ gen_movl_T0_reg(rd);
+ break;
+ case 0x3d: /* restore */
+ save_state(dc);
+ gen_op_restore();
+ gen_movl_T0_reg(rd);
+ break;
#if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
- case 0x3e: /* V9 done/retry */
- {
- switch (rd) {
- case 0:
- if (!supervisor(dc))
- goto priv_insn;
- dc->npc = DYNAMIC_PC;
- dc->pc = DYNAMIC_PC;
- gen_op_done();
- goto jmp_insn;
- case 1:
- if (!supervisor(dc))
- goto priv_insn;
- dc->npc = DYNAMIC_PC;
- dc->pc = DYNAMIC_PC;
- gen_op_retry();
- goto jmp_insn;
- default:
- goto illegal_insn;
- }
- }
- break;
-#endif
- default:
- goto illegal_insn;
- }
+ case 0x3e: /* V9 done/retry */
+ {
+ switch (rd) {
+ case 0:
+ if (!supervisor(dc))
+ goto priv_insn;
+ dc->npc = DYNAMIC_PC;
+ dc->pc = DYNAMIC_PC;
+ gen_op_done();
+ goto jmp_insn;
+ case 1:
+ if (!supervisor(dc))
+ goto priv_insn;
+ dc->npc = DYNAMIC_PC;
+ dc->pc = DYNAMIC_PC;
+ gen_op_retry();
+ goto jmp_insn;
+ default:
+ goto illegal_insn;
+ }
+ }
+ break;
+#endif
+ default:
+ goto illegal_insn;
+ }
}
- break;
- }
- break;
- case 3: /* load/store instructions */
- {
- unsigned int xop = GET_FIELD(insn, 7, 12);
- rs1 = GET_FIELD(insn, 13, 17);
+ break;
+ }
+ break;
+ case 3: /* load/store instructions */
+ {
+ unsigned int xop = GET_FIELD(insn, 7, 12);
+ rs1 = GET_FIELD(insn, 13, 17);
save_state(dc);
- gen_movl_reg_T0(rs1);
- if (IS_IMM) { /* immediate */
- rs2 = GET_FIELDs(insn, 19, 31);
+ gen_movl_reg_T0(rs1);
+ if (IS_IMM) { /* immediate */
+ rs2 = GET_FIELDs(insn, 19, 31);
#if defined(OPTIM)
- if (rs2 != 0) {
+ if (rs2 != 0) {
#endif
- gen_movl_simm_T1(rs2);
- gen_op_add_T1_T0();
+ gen_movl_simm_T1(rs2);
+ gen_op_add_T1_T0();
#if defined(OPTIM)
- }
+ }
#endif
- } else { /* register */
- rs2 = GET_FIELD(insn, 27, 31);
+ } else { /* register */
+ rs2 = GET_FIELD(insn, 27, 31);
#if defined(OPTIM)
- if (rs2 != 0) {
+ if (rs2 != 0) {
#endif
- gen_movl_reg_T1(rs2);
- gen_op_add_T1_T0();
+ gen_movl_reg_T1(rs2);
+ gen_op_add_T1_T0();
#if defined(OPTIM)
- }
+ }
#endif
- }
+ }
if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) ||
(xop > 0x17 && xop <= 0x1d ) ||
(xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) {
- switch (xop) {
- case 0x0: /* load word */
+ switch (xop) {
+ case 0x0: /* load word */
#ifdef CONFIG_USER_ONLY
gen_op_check_align_T0_3();
#endif
#ifndef TARGET_SPARC64
- gen_op_ldst(ld);
+ gen_op_ldst(ld);
#else
gen_op_ldst(lduw);
#endif
- break;
- case 0x1: /* load unsigned byte */
- gen_op_ldst(ldub);
- break;
- case 0x2: /* load unsigned halfword */
+ break;
+ case 0x1: /* load unsigned byte */
+ gen_op_ldst(ldub);
+ break;
+ case 0x2: /* load unsigned halfword */
#ifdef CONFIG_USER_ONLY
gen_op_check_align_T0_1();
#endif
- gen_op_ldst(lduh);
- break;
- case 0x3: /* load double word */
+ gen_op_ldst(lduh);
+ break;
+ case 0x3: /* load double word */
gen_op_check_align_T0_7();
- if (rd & 1)
+ if (rd & 1)
goto illegal_insn;
- gen_op_ldst(ldd);
- gen_movl_T0_reg(rd + 1);
- break;
- case 0x9: /* load signed byte */
- gen_op_ldst(ldsb);
- break;
- case 0xa: /* load signed halfword */
+ gen_op_ldst(ldd);
+ gen_movl_T0_reg(rd + 1);
+ break;
+ case 0x9: /* load signed byte */
+ gen_op_ldst(ldsb);
+ break;
+ case 0xa: /* load signed halfword */
#ifdef CONFIG_USER_ONLY
gen_op_check_align_T0_1();
#endif
- gen_op_ldst(ldsh);
- break;
- case 0xd: /* ldstub -- XXX: should be atomically */
- gen_op_ldst(ldstub);
- break;
- case 0x0f: /* swap register with memory. Also atomically */
+ gen_op_ldst(ldsh);
+ break;
+ case 0xd: /* ldstub -- XXX: should be atomically */
+ gen_op_ldst(ldstub);
+ break;
+ case 0x0f: /* swap register with memory. Also atomically */
#ifdef CONFIG_USER_ONLY
gen_op_check_align_T0_3();
#endif
- gen_movl_reg_T1(rd);
- gen_op_ldst(swap);
- break;
+ gen_movl_reg_T1(rd);
+ gen_op_ldst(swap);
+ break;
#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
- case 0x10: /* load word alternate */
+ case 0x10: /* load word alternate */
#ifndef TARGET_SPARC64
- if (IS_IMM)
- goto illegal_insn;
- if (!supervisor(dc))
- goto priv_insn;
+ if (IS_IMM)
+ goto illegal_insn;
+ if (!supervisor(dc))
+ goto priv_insn;
#ifdef CONFIG_USER_ONLY
gen_op_check_align_T0_3();
#endif
- gen_op_lda(insn, 1, 4, 0);
+ gen_op_lda(insn, 1, 4, 0);
#else
#ifdef CONFIG_USER_ONLY
gen_op_check_align_T0_3();
#endif
gen_op_lduwa(insn, 1, 4, 0);
#endif
- break;
- case 0x11: /* load unsigned byte alternate */
+ break;
+ case 0x11: /* load unsigned byte alternate */
#ifndef TARGET_SPARC64
- if (IS_IMM)
- goto illegal_insn;
- if (!supervisor(dc))
- goto priv_insn;
-#endif
- gen_op_lduba(insn, 1, 1, 0);
- break;
- case 0x12: /* load unsigned halfword alternate */
+ if (IS_IMM)
+ goto illegal_insn;
+ if (!supervisor(dc))
+ goto priv_insn;
+#endif
+ gen_op_lduba(insn, 1, 1, 0);
+ break;
+ case 0x12: /* load unsigned halfword alternate */
#ifndef TARGET_SPARC64
- if (IS_IMM)
- goto illegal_insn;
- if (!supervisor(dc))
- goto priv_insn;
+ if (IS_IMM)
+ goto illegal_insn;
+ if (!supervisor(dc))
+ goto priv_insn;
#endif
#ifdef CONFIG_USER_ONLY
gen_op_check_align_T0_1();
#endif
- gen_op_lduha(insn, 1, 2, 0);
- break;
- case 0x13: /* load double word alternate */
+ gen_op_lduha(insn, 1, 2, 0);
+ break;
+ case 0x13: /* load double word alternate */
#ifndef TARGET_SPARC64
- if (IS_IMM)
- goto illegal_insn;
- if (!supervisor(dc))
- goto priv_insn;
+ if (IS_IMM)
+ goto illegal_insn;
+ if (!supervisor(dc))
+ goto priv_insn;
#endif
- if (rd & 1)
+ if (rd & 1)
goto illegal_insn;
gen_op_check_align_T0_7();
- gen_op_ldda(insn, 1, 8, 0);
- gen_movl_T0_reg(rd + 1);
- break;
- case 0x19: /* load signed byte alternate */
+ gen_op_ldda(insn, 1, 8, 0);
+ gen_movl_T0_reg(rd + 1);
+ break;
+ case 0x19: /* load signed byte alternate */
#ifndef TARGET_SPARC64
- if (IS_IMM)
- goto illegal_insn;
- if (!supervisor(dc))
- goto priv_insn;
-#endif
- gen_op_ldsba(insn, 1, 1, 1);
- break;
- case 0x1a: /* load signed halfword alternate */
+ if (IS_IMM)
+ goto illegal_insn;
+ if (!supervisor(dc))
+ goto priv_insn;
+#endif
+ gen_op_ldsba(insn, 1, 1, 1);
+ break;
+ case 0x1a: /* load signed halfword alternate */
#ifndef TARGET_SPARC64
- if (IS_IMM)
- goto illegal_insn;
- if (!supervisor(dc))
- goto priv_insn;
+ if (IS_IMM)
+ goto illegal_insn;
+ if (!supervisor(dc))
+ goto priv_insn;
#endif
#ifdef CONFIG_USER_ONLY
gen_op_check_align_T0_1();
#endif
- gen_op_ldsha(insn, 1, 2 ,1);
- break;
- case 0x1d: /* ldstuba -- XXX: should be atomically */
+ gen_op_ldsha(insn, 1, 2 ,1);
+ break;
+ case 0x1d: /* ldstuba -- XXX: should be atomically */
#ifndef TARGET_SPARC64
- if (IS_IMM)
- goto illegal_insn;
- if (!supervisor(dc))
- goto priv_insn;
-#endif
- gen_op_ldstuba(insn, 1, 1, 0);
- break;
- case 0x1f: /* swap reg with alt. memory. Also atomically */
+ if (IS_IMM)
+ goto illegal_insn;
+ if (!supervisor(dc))
+ goto priv_insn;
+#endif
+ gen_op_ldstuba(insn, 1, 1, 0);
+ break;
+ case 0x1f: /* swap reg with alt. memory. Also atomically */
#ifndef TARGET_SPARC64
- if (IS_IMM)
- goto illegal_insn;
- if (!supervisor(dc))
- goto priv_insn;
+ if (IS_IMM)
+ goto illegal_insn;
+ if (!supervisor(dc))
+ goto priv_insn;
#endif
- gen_movl_reg_T1(rd);
+ gen_movl_reg_T1(rd);
#ifdef CONFIG_USER_ONLY
gen_op_check_align_T0_3();
#endif
- gen_op_swapa(insn, 1, 4, 0);
- break;
+ gen_op_swapa(insn, 1, 4, 0);
+ break;
#ifndef TARGET_SPARC64
- case 0x30: /* ldc */
- case 0x31: /* ldcsr */
- case 0x33: /* lddc */
- goto ncp_insn;
+ case 0x30: /* ldc */
+ case 0x31: /* ldcsr */
+ case 0x33: /* lddc */
+ goto ncp_insn;
/* avoid warnings */
(void) &gen_op_stfa;
(void) &gen_op_stdfa;
@@ -2975,260 +2975,260 @@ static void disas_sparc_insn(DisasContext * dc)
#else
(void) &gen_op_lda;
#if !defined(CONFIG_USER_ONLY)
- (void) &gen_op_cas;
- (void) &gen_op_casx;
+ (void) &gen_op_cas;
+ (void) &gen_op_casx;
#endif
#endif
#endif
#ifdef TARGET_SPARC64
- case 0x08: /* V9 ldsw */
+ case 0x08: /* V9 ldsw */
#ifdef CONFIG_USER_ONLY
gen_op_check_align_T0_3();
#endif
- gen_op_ldst(ldsw);
- break;
- case 0x0b: /* V9 ldx */
+ gen_op_ldst(ldsw);
+ break;
+ case 0x0b: /* V9 ldx */
gen_op_check_align_T0_7();
- gen_op_ldst(ldx);
- break;
- case 0x18: /* V9 ldswa */
+ gen_op_ldst(ldx);
+ break;
+ case 0x18: /* V9 ldswa */
#ifdef CONFIG_USER_ONLY
gen_op_check_align_T0_3();
#endif
- gen_op_ldswa(insn, 1, 4, 1);
- break;
- case 0x1b: /* V9 ldxa */
+ gen_op_ldswa(insn, 1, 4, 1);
+ break;
+ case 0x1b: /* V9 ldxa */
gen_op_check_align_T0_7();
- gen_op_ldxa(insn, 1, 8, 0);
- break;
- case 0x2d: /* V9 prefetch, no effect */
- goto skip_move;
- case 0x30: /* V9 ldfa */
+ gen_op_ldxa(insn, 1, 8, 0);
+ break;
+ case 0x2d: /* V9 prefetch, no effect */
+ goto skip_move;
+ case 0x30: /* V9 ldfa */
#ifdef CONFIG_USER_ONLY
gen_op_check_align_T0_3();
#endif
- gen_op_ldfa(insn, 1, 8, 0); // XXX
- break;
- case 0x33: /* V9 lddfa */
+ gen_op_ldfa(insn, 1, 8, 0); // XXX
+ break;
+ case 0x33: /* V9 lddfa */
gen_op_check_align_T0_7();
- gen_op_lddfa(insn, 1, 8, 0); // XXX
-
- break;
- case 0x3d: /* V9 prefetcha, no effect */
- goto skip_move;
- case 0x32: /* V9 ldqfa */
- goto nfpu_insn;
-#endif
- default:
- goto illegal_insn;
- }
- gen_movl_T1_reg(rd);
+ gen_op_lddfa(insn, 1, 8, 0); // XXX
+
+ break;
+ case 0x3d: /* V9 prefetcha, no effect */
+ goto skip_move;
+ case 0x32: /* V9 ldqfa */
+ goto nfpu_insn;
+#endif
+ default:
+ goto illegal_insn;
+ }
+ gen_movl_T1_reg(rd);
#ifdef TARGET_SPARC64
- skip_move: ;
+ skip_move: ;
#endif
- } else if (xop >= 0x20 && xop < 0x24) {
+ } else if (xop >= 0x20 && xop < 0x24) {
if (gen_trap_ifnofpu(dc))
goto jmp_insn;
- switch (xop) {
- case 0x20: /* load fpreg */
+ switch (xop) {
+ case 0x20: /* load fpreg */
#ifdef CONFIG_USER_ONLY
gen_op_check_align_T0_3();
#endif
- gen_op_ldst(ldf);
- gen_op_store_FT0_fpr(rd);
- break;
- case 0x21: /* load fsr */
+ gen_op_ldst(ldf);
+ gen_op_store_FT0_fpr(rd);
+ break;
+ case 0x21: /* load fsr */
#ifdef CONFIG_USER_ONLY
gen_op_check_align_T0_3();
#endif
- gen_op_ldst(ldf);
- gen_op_ldfsr();
- break;
- case 0x22: /* load quad fpreg */
- goto nfpu_insn;
- case 0x23: /* load double fpreg */
+ gen_op_ldst(ldf);
+ gen_op_ldfsr();
+ break;
+ case 0x22: /* load quad fpreg */
+ goto nfpu_insn;
+ case 0x23: /* load double fpreg */
gen_op_check_align_T0_7();
- gen_op_ldst(lddf);
- gen_op_store_DT0_fpr(DFPREG(rd));
- break;
- default:
- goto illegal_insn;
- }
- } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) || \
- xop == 0xe || xop == 0x1e) {
- gen_movl_reg_T1(rd);
- switch (xop) {
- case 0x4:
+ gen_op_ldst(lddf);
+ gen_op_store_DT0_fpr(DFPREG(rd));
+ break;
+ default:
+ goto illegal_insn;
+ }
+ } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) || \
+ xop == 0xe || xop == 0x1e) {
+ gen_movl_reg_T1(rd);
+ switch (xop) {
+ case 0x4:
#ifdef CONFIG_USER_ONLY
gen_op_check_align_T0_3();
#endif
- gen_op_ldst(st);
- break;
- case 0x5:
- gen_op_ldst(stb);
- break;
- case 0x6:
+ gen_op_ldst(st);
+ break;
+ case 0x5:
+ gen_op_ldst(stb);
+ break;
+ case 0x6:
#ifdef CONFIG_USER_ONLY
gen_op_check_align_T0_1();
#endif
- gen_op_ldst(sth);
- break;
- case 0x7:
- if (rd & 1)
+ gen_op_ldst(sth);
+ break;
+ case 0x7:
+ if (rd & 1)
goto illegal_insn;
gen_op_check_align_T0_7();
flush_T2(dc);
- gen_movl_reg_T2(rd + 1);
- gen_op_ldst(std);
- break;
+ gen_movl_reg_T2(rd + 1);
+ gen_op_ldst(std);
+ break;
#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
- case 0x14:
+ case 0x14:
#ifndef TARGET_SPARC64
- if (IS_IMM)
- goto illegal_insn;
- if (!supervisor(dc))
- goto priv_insn;
+ if (IS_IMM)
+ goto illegal_insn;
+ if (!supervisor(dc))
+ goto priv_insn;
#endif
#ifdef CONFIG_USER_ONLY
gen_op_check_align_T0_3();
#endif
- gen_op_sta(insn, 0, 4, 0);
+ gen_op_sta(insn, 0, 4, 0);
break;
- case 0x15:
+ case 0x15:
#ifndef TARGET_SPARC64
- if (IS_IMM)
- goto illegal_insn;
- if (!supervisor(dc))
- goto priv_insn;
+ if (IS_IMM)
+ goto illegal_insn;
+ if (!supervisor(dc))
+ goto priv_insn;
#endif
- gen_op_stba(insn, 0, 1, 0);
+ gen_op_stba(insn, 0, 1, 0);
break;
- case 0x16:
+ case 0x16:
#ifndef TARGET_SPARC64
- if (IS_IMM)
- goto illegal_insn;
- if (!supervisor(dc))
- goto priv_insn;
+ if (IS_IMM)
+ goto illegal_insn;
+ if (!supervisor(dc))
+ goto priv_insn;
#endif
#ifdef CONFIG_USER_ONLY
gen_op_check_align_T0_1();
#endif
- gen_op_stha(insn, 0, 2, 0);
+ gen_op_stha(insn, 0, 2, 0);
break;
- case 0x17:
+ case 0x17:
#ifndef TARGET_SPARC64
- if (IS_IMM)
- goto illegal_insn;
- if (!supervisor(dc))
- goto priv_insn;
+ if (IS_IMM)
+ goto illegal_insn;
+ if (!supervisor(dc))
+ goto priv_insn;
#endif
- if (rd & 1)
+ if (rd & 1)
goto illegal_insn;
gen_op_check_align_T0_7();
flush_T2(dc);
- gen_movl_reg_T2(rd + 1);
- gen_op_stda(insn, 0, 8, 0);
+ gen_movl_reg_T2(rd + 1);
+ gen_op_stda(insn, 0, 8, 0);
break;
#endif
#ifdef TARGET_SPARC64
- case 0x0e: /* V9 stx */
+ case 0x0e: /* V9 stx */
gen_op_check_align_T0_7();
- gen_op_ldst(stx);
- break;
- case 0x1e: /* V9 stxa */
+ gen_op_ldst(stx);
+ break;
+ case 0x1e: /* V9 stxa */
gen_op_check_align_T0_7();
- gen_op_stxa(insn, 0, 8, 0); // XXX
- break;
+ gen_op_stxa(insn, 0, 8, 0); // XXX
+ break;
#endif
- default:
- goto illegal_insn;
- }
- } else if (xop > 0x23 && xop < 0x28) {
+ default:
+ goto illegal_insn;
+ }
+ } else if (xop > 0x23 && xop < 0x28) {
if (gen_trap_ifnofpu(dc))
goto jmp_insn;
- switch (xop) {
- case 0x24:
+ switch (xop) {
+ case 0x24:
#ifdef CONFIG_USER_ONLY
gen_op_check_align_T0_3();
#endif
gen_op_load_fpr_FT0(rd);
- gen_op_ldst(stf);
- break;
- case 0x25: /* stfsr, V9 stxfsr */
+ gen_op_ldst(stf);
+ break;
+ case 0x25: /* stfsr, V9 stxfsr */
#ifdef CONFIG_USER_ONLY
gen_op_check_align_T0_3();
#endif
- gen_op_stfsr();
- gen_op_ldst(stf);
- break;
+ gen_op_stfsr();
+ gen_op_ldst(stf);
+ break;
#if !defined(CONFIG_USER_ONLY)
- case 0x26: /* stdfq */
- if (!supervisor(dc))
- goto priv_insn;
- if (gen_trap_ifnofpu(dc))
- goto jmp_insn;
- goto nfq_insn;
-#endif
- case 0x27:
+ case 0x26: /* stdfq */
+ if (!supervisor(dc))
+ goto priv_insn;
+ if (gen_trap_ifnofpu(dc))
+ goto jmp_insn;
+ goto nfq_insn;
+#endif
+ case 0x27:
gen_op_check_align_T0_7();
gen_op_load_fpr_DT0(DFPREG(rd));
- gen_op_ldst(stdf);
- break;
- default:
- goto illegal_insn;
- }
- } else if (xop > 0x33 && xop < 0x3f) {
- switch (xop) {
+ gen_op_ldst(stdf);
+ break;
+ default:
+ goto illegal_insn;
+ }
+ } else if (xop > 0x33 && xop < 0x3f) {
+ switch (xop) {
#ifdef TARGET_SPARC64
- case 0x34: /* V9 stfa */
+ case 0x34: /* V9 stfa */
#ifdef CONFIG_USER_ONLY
gen_op_check_align_T0_3();
#endif
- gen_op_stfa(insn, 0, 0, 0); // XXX
- break;
- case 0x37: /* V9 stdfa */
+ gen_op_stfa(insn, 0, 0, 0); // XXX
+ break;
+ case 0x37: /* V9 stdfa */
gen_op_check_align_T0_7();
- gen_op_stdfa(insn, 0, 0, 0); // XXX
- break;
- case 0x3c: /* V9 casa */
+ gen_op_stdfa(insn, 0, 0, 0); // XXX
+ break;
+ case 0x3c: /* V9 casa */
#ifdef CONFIG_USER_ONLY
gen_op_check_align_T0_3();
#endif
- gen_op_casa(insn, 0, 4, 0); // XXX
- break;
- case 0x3e: /* V9 casxa */
+ gen_op_casa(insn, 0, 4, 0); // XXX
+ break;
+ case 0x3e: /* V9 casxa */
gen_op_check_align_T0_7();
- gen_op_casxa(insn, 0, 8, 0); // XXX
- break;
- case 0x36: /* V9 stqfa */
- goto nfpu_insn;
+ gen_op_casxa(insn, 0, 8, 0); // XXX
+ break;
+ case 0x36: /* V9 stqfa */
+ goto nfpu_insn;
#else
- case 0x34: /* stc */
- case 0x35: /* stcsr */
- case 0x36: /* stdcq */
- case 0x37: /* stdc */
- goto ncp_insn;
-#endif
- default:
- goto illegal_insn;
- }
+ case 0x34: /* stc */
+ case 0x35: /* stcsr */
+ case 0x36: /* stdcq */
+ case 0x37: /* stdc */
+ goto ncp_insn;
+#endif
+ default:
+ goto illegal_insn;
+ }
}
- else
- goto illegal_insn;
- }
- break;
+ else
+ goto illegal_insn;
+ }
+ break;
}
/* default case for non jump instructions */
if (dc->npc == DYNAMIC_PC) {
- dc->pc = DYNAMIC_PC;
- gen_op_next_insn();
+ dc->pc = DYNAMIC_PC;
+ gen_op_next_insn();
} else if (dc->npc == JUMP_PC) {
/* we can do a static jump */
gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1]);
dc->is_br = 1;
} else {
- dc->pc = dc->npc;
- dc->npc = dc->npc + 4;
+ dc->pc = dc->npc;
+ dc->npc = dc->npc + 4;
}
jmp_insn:
return;
@@ -3266,7 +3266,7 @@ static void disas_sparc_insn(DisasContext * dc)
}
static inline int gen_intermediate_code_internal(TranslationBlock * tb,
- int spc, CPUSPARCState *env)
+ int spc, CPUSPARCState *env)
{
target_ulong pc_start, last_pc;
uint16_t *gen_opc_end;
@@ -3299,12 +3299,12 @@ static inline int gen_intermediate_code_internal(TranslationBlock * tb,
if (env->nb_breakpoints > 0) {
for(j = 0; j < env->nb_breakpoints; j++) {
if (env->breakpoints[j] == dc->pc) {
- if (dc->pc != pc_start)
- save_state(dc);
+ if (dc->pc != pc_start)
+ save_state(dc);
gen_op_debug();
- gen_op_movl_T0_0();
- gen_op_exit_tb();
- dc->is_br = 1;
+ gen_op_movl_T0_0();
+ gen_op_exit_tb();
+ dc->is_br = 1;
goto exit_gen_loop;
}
}
@@ -3322,14 +3322,14 @@ static inline int gen_intermediate_code_internal(TranslationBlock * tb,
gen_opc_instr_start[lj] = 1;
}
}
- last_pc = dc->pc;
- disas_sparc_insn(dc);
-
- if (dc->is_br)
- break;
- /* if the next PC is different, we abort now */
- if (dc->pc != (last_pc + 4))
- break;
+ last_pc = dc->pc;
+ disas_sparc_insn(dc);
+
+ if (dc->is_br)
+ break;
+ /* if the next PC is different, we abort now */
+ if (dc->pc != (last_pc + 4))
+ break;
/* if we reach a page boundary, we stop generation so that the
PC of a TT_TFAULT exception is always in the right page */
if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0)
@@ -3343,7 +3343,7 @@ static inline int gen_intermediate_code_internal(TranslationBlock * tb,
break;
}
} while ((gen_opc_ptr < gen_opc_end) &&
- (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32));
+ (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32));
exit_gen_loop:
if (!dc->is_br) {
@@ -3377,10 +3377,10 @@ static inline int gen_intermediate_code_internal(TranslationBlock * tb,
}
#ifdef DEBUG_DISAS
if (loglevel & CPU_LOG_TB_IN_ASM) {
- fprintf(logfile, "--------------\n");
- fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
- target_disas(logfile, pc_start, last_pc + 4 - pc_start, 0);
- fprintf(logfile, "\n");
+ fprintf(logfile, "--------------\n");
+ fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
+ target_disas(logfile, pc_start, last_pc + 4 - pc_start, 0);
+ fprintf(logfile, "\n");
if (loglevel & CPU_LOG_TB_OP) {
fprintf(logfile, "OP:\n");
dump_ops(gen_opc_buf, gen_opparam_buf);
@@ -3438,7 +3438,7 @@ CPUSPARCState *cpu_sparc_init(void)
env = qemu_mallocz(sizeof(CPUSPARCState));
if (!env)
- return NULL;
+ return NULL;
cpu_exec_init(env);
cpu_reset(env);
return (env);
@@ -3539,22 +3539,22 @@ void cpu_dump_state(CPUState *env, FILE *f,
cpu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc, env->npc);
cpu_fprintf(f, "General Registers:\n");
for (i = 0; i < 4; i++)
- cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
+ cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
cpu_fprintf(f, "\n");
for (; i < 8; i++)
- cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
+ cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
cpu_fprintf(f, "\nCurrent Register Window:\n");
for (x = 0; x < 3; x++) {
- for (i = 0; i < 4; i++)
- cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
- (x == 0 ? 'o' : (x == 1 ? 'l' : 'i')), i,
- env->regwptr[i + x * 8]);
- cpu_fprintf(f, "\n");
- for (; i < 8; i++)
- cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
- (x == 0 ? 'o' : x == 1 ? 'l' : 'i'), i,
- env->regwptr[i + x * 8]);
- cpu_fprintf(f, "\n");
+ for (i = 0; i < 4; i++)
+ cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
+ (x == 0 ? 'o' : (x == 1 ? 'l' : 'i')), i,
+ env->regwptr[i + x * 8]);
+ cpu_fprintf(f, "\n");
+ for (; i < 8; i++)
+ cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
+ (x == 0 ? 'o' : x == 1 ? 'l' : 'i'), i,
+ env->regwptr[i + x * 8]);
+ cpu_fprintf(f, "\n");
}
cpu_fprintf(f, "\nFloating Point Registers:\n");
for (i = 0; i < 32; i++) {
@@ -3566,16 +3566,16 @@ void cpu_dump_state(CPUState *env, FILE *f,
}
#ifdef TARGET_SPARC64
cpu_fprintf(f, "pstate: 0x%08x ccr: 0x%02x asi: 0x%02x tl: %d fprs: %d\n",
- env->pstate, GET_CCR(env), env->asi, env->tl, env->fprs);
+ env->pstate, GET_CCR(env), env->asi, env->tl, env->fprs);
cpu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate %d cleanwin %d cwp %d\n",
- env->cansave, env->canrestore, env->otherwin, env->wstate,
- env->cleanwin, NWINDOWS - 1 - env->cwp);
+ env->cansave, env->canrestore, env->otherwin, env->wstate,
+ env->cleanwin, NWINDOWS - 1 - env->cwp);
#else
cpu_fprintf(f, "psr: 0x%08x -> %c%c%c%c %c%c%c wim: 0x%08x\n", GET_PSR(env),
- GET_FLAG(PSR_ZERO, 'Z'), GET_FLAG(PSR_OVF, 'V'),
- GET_FLAG(PSR_NEG, 'N'), GET_FLAG(PSR_CARRY, 'C'),
- env->psrs?'S':'-', env->psrps?'P':'-',
- env->psret?'E':'-', env->wim);
+ GET_FLAG(PSR_ZERO, 'Z'), GET_FLAG(PSR_OVF, 'V'),
+ GET_FLAG(PSR_NEG, 'N'), GET_FLAG(PSR_CARRY, 'C'),
+ env->psrs?'S':'-', env->psrps?'P':'-',
+ env->psret?'E':'-', env->wim);
#endif
cpu_fprintf(f, "fsr: 0x%08x\n", GET_FSR32(env));
}
generated by cgit v1.2.1 (git 2.18.0) at 2024-07-05 03:21:38 +0000