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| author | blueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-04-06 20:02:09 +0000 |
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| committer | blueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-04-06 20:02:09 +0000 |
| commit | c185970a0e3c72b5f70bad599c4160d037427c81 (patch) | |
| tree | 9101ad7fb5164696b703c04eab5c1cfcc1a87107 /target-sparc/translate.c | |
| parent | beb811bdd693ff1e2fe5c6c81e65b0b8e9053755 (diff) | |
| download | qemu-c185970a0e3c72b5f70bad599c4160d037427c81.tar.gz | |
Enforce even float register pair for double register ops (Aurelien Jarno)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2624 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-sparc/translate.c')
| -rw-r--r-- | target-sparc/translate.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target-sparc/translate.c b/target-sparc/translate.c index cb11b928f6..34a3357f97 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -90,7 +90,7 @@ enum { #ifdef TARGET_SPARC64 #define DFPREG(r) (((r & 1) << 6) | (r & 0x1e)) #else -#define DFPREG(r) (r) +#define DFPREG(r) (r & 0x1e) #endif #ifdef USE_DIRECT_JUMP |