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authorBastian Koppelmann <kbastian@mail.uni-paderborn.de>2016-02-16 22:27:32 +0100
committerBastian Koppelmann <kbastian@mail.uni-paderborn.de>2016-02-25 12:51:31 +0100
commit5dc1fbae707513f9664aa88940a2cd52b064cda2 (patch)
treee9c4aba52ae531b10ba52ab0aaba65b204cc1cf7 /target-tricore
parent723733575b90089c51adefde41875310052031c2 (diff)
downloadqemu-5dc1fbae707513f9664aa88940a2cd52b064cda2.tar.gz
target-tricore: Fix wrong precedences on psw_write
Wrong braces on the restore of the cached TCGv SV and V bit could lead to a wrong PSW. While at this it removes unnecessary braces for the restore of the cached TCGv AV and SAV bits. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Diffstat (limited to 'target-tricore')
-rw-r--r--target-tricore/helper.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/target-tricore/helper.c b/target-tricore/helper.c
index a8fd418b42..7d96daddb1 100644
--- a/target-tricore/helper.c
+++ b/target-tricore/helper.c
@@ -127,9 +127,9 @@ uint32_t psw_read(CPUTriCoreState *env)
void psw_write(CPUTriCoreState *env, uint32_t val)
{
env->PSW_USB_C = (val & MASK_USB_C);
- env->PSW_USB_V = (val & MASK_USB_V << 1);
- env->PSW_USB_SV = (val & MASK_USB_SV << 2);
- env->PSW_USB_AV = ((val & MASK_USB_AV) << 3);
- env->PSW_USB_SAV = ((val & MASK_USB_SAV) << 4);
+ env->PSW_USB_V = (val & MASK_USB_V) << 1;
+ env->PSW_USB_SV = (val & MASK_USB_SV) << 2;
+ env->PSW_USB_AV = (val & MASK_USB_AV) << 3;
+ env->PSW_USB_SAV = (val & MASK_USB_SAV) << 4;
env->PSW = val;
}