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| author | Max Filippov <jcmvbkbc@gmail.com> | 2012-09-19 04:23:54 +0400 |
|---|---|---|
| committer | Blue Swirl <blauwirbel@gmail.com> | 2012-09-22 17:59:12 +0000 |
| commit | dd519cbec63434f2b883f0b4a20f827bbd59793e (patch) | |
| tree | 703e0fae97159346ca18b6edfe4c895f7e343570 /target-xtensa/cpu.h | |
| parent | b81fe822dad134871cd336e26ed55d165e597f4e (diff) | |
| download | qemu-dd519cbec63434f2b883f0b4a20f827bbd59793e.tar.gz | |
target-xtensa: add FP registers
There are 16 32-bit FP registers (f0 - f15), control and status user
registers (fcr, fsr).
See ISA, 4.3.10 for more details.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Diffstat (limited to 'target-xtensa/cpu.h')
| -rw-r--r-- | target-xtensa/cpu.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h index 177094ae9a..b4562832b3 100644 --- a/target-xtensa/cpu.h +++ b/target-xtensa/cpu.h @@ -36,6 +36,7 @@ #include "config.h" #include "qemu-common.h" #include "cpu-defs.h" +#include "fpu/softfloat.h" #define TARGET_HAS_ICE 1 @@ -325,6 +326,8 @@ typedef struct CPUXtensaState { uint32_t sregs[256]; uint32_t uregs[256]; uint32_t phys_regs[MAX_NAREG]; + float32 fregs[16]; + float_status fp_status; xtensa_tlb_entry itlb[7][MAX_TLB_WAY_SIZE]; xtensa_tlb_entry dtlb[10][MAX_TLB_WAY_SIZE]; |