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| author | Alex Bennée <alex.bennee@linaro.org> | 2018-03-01 11:05:48 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2018-03-01 11:13:59 +0000 |
| commit | 807cdd504283c11addcd7ea95ba594bbddc86fe4 (patch) | |
| tree | aea3cddf23b332791785f3c23668f268ddab096d /target/arm/helper-a64.c | |
| parent | 9b04991686785e18b18a36d193b68f08f7c91648 (diff) | |
| download | qemu-807cdd504283c11addcd7ea95ba594bbddc86fe4.tar.gz | |
arm/translate-a64: implement half-precision F(MIN|MAX)(V|NMV)
This implements the half-precision variants of the across vector
reduction operations. This involves a re-factor of the reduction code
which more closely matches the ARM ARM order (and handles 8 element
reductions).
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180227143852.11175-7-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/helper-a64.c')
| -rw-r--r-- | target/arm/helper-a64.c | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 10e08bdc1f..fddd5d242b 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -572,3 +572,21 @@ uint64_t HELPER(paired_cmpxchg64_be_parallel)(CPUARMState *env, uint64_t addr, { return do_paired_cmpxchg64_be(env, addr, new_lo, new_hi, true, GETPC()); } + +/* + * AdvSIMD half-precision + */ + +#define ADVSIMD_HELPER(name, suffix) HELPER(glue(glue(advsimd_, name), suffix)) + +#define ADVSIMD_HALFOP(name) \ +float16 ADVSIMD_HELPER(name, h)(float16 a, float16 b, void *fpstp) \ +{ \ + float_status *fpst = fpstp; \ + return float16_ ## name(a, b, fpst); \ +} + +ADVSIMD_HALFOP(min) +ADVSIMD_HALFOP(max) +ADVSIMD_HALFOP(minnum) +ADVSIMD_HALFOP(maxnum) |