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| author | Peter Maydell <peter.maydell@linaro.org> | 2018-02-06 10:39:41 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2018-02-09 10:55:39 +0000 |
| commit | 384c6c03fb687bea239a5990a538c4bc50fdcecb (patch) | |
| tree | 3418155b8bae822066c7df9a7378f50eea6f08b5 /target/arm/translate.c | |
| parent | bd55947884b5421697d186016b0e57b1d6643fe0 (diff) | |
| download | qemu-384c6c03fb687bea239a5990a538c4bc50fdcecb.tar.gz | |
target/arm/translate.c: Fix missing 'break' for TT insns
The code where we added the TT instruction was accidentally
missing a 'break', which meant that after generating the code
to execute the TT we would fall through to 'goto illegal_op'
and generate code to take an UNDEF insn.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20180206103941.13985-1-peter.maydell@linaro.org
Diffstat (limited to 'target/arm/translate.c')
| -rw-r--r-- | target/arm/translate.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/arm/translate.c b/target/arm/translate.c index a8c13d3758..1270022289 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9925,6 +9925,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) tcg_temp_free_i32(addr); tcg_temp_free_i32(op); store_reg(s, rd, ttresp); + break; } goto illegal_op; } |