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| author | Richard Henderson <richard.henderson@linaro.org> | 2017-11-02 15:19:14 +0100 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2017-12-29 12:43:39 -0800 |
| commit | 15fa08f8451babc88d733bd411d4c94976f9d0f8 (patch) | |
| tree | 2db297c71e5e7a9f9ae5cff3d37bb98d2b724898 /target/arm/translate.h | |
| parent | f764718d0cb30af9f1f8e1d6a33622cc05ca4155 (diff) | |
| download | qemu-15fa08f8451babc88d733bd411d4c94976f9d0f8.tar.gz | |
tcg: Dynamically allocate TCGOps
With no fixed array allocation, we can't overflow a buffer.
This will be important as optimizations related to host vectors
may expand the number of ops used.
Use QTAILQ to link the ops together.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/arm/translate.h')
| -rw-r--r-- | target/arm/translate.h | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/target/arm/translate.h b/target/arm/translate.h index 410ba79c0d..cd7313ace7 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -66,8 +66,8 @@ typedef struct DisasContext { bool ss_same_el; /* Bottom two bits of XScale c15_cpar coprocessor access control reg */ int c15_cpar; - /* TCG op index of the current insn_start. */ - int insn_start_idx; + /* TCG op of the current insn_start. */ + TCGOp *insn_start; #define TMP_A64_MAX 16 int tmp_a64_count; TCGv_i64 tmp_a64[TMP_A64_MAX]; @@ -117,9 +117,9 @@ static void disas_set_insn_syndrome(DisasContext *s, uint32_t syn) syn >>= ARM_INSN_START_WORD2_SHIFT; /* We check and clear insn_start_idx to catch multiple updates. */ - assert(s->insn_start_idx != 0); - tcg_set_insn_param(s->insn_start_idx, 2, syn); - s->insn_start_idx = 0; + assert(s->insn_start != NULL); + tcg_set_insn_param(s->insn_start, 2, syn); + s->insn_start = NULL; } /* is_jmp field values */ |