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| author | Lluís Vilanova <vilanova@ac.upc.edu> | 2017-07-14 11:17:35 +0300 |
|---|---|---|
| committer | Richard Henderson <rth@twiddle.net> | 2017-07-19 14:45:16 -0700 |
| commit | 9c489ea6bed134fecfd556b439c68bba48fbe102 (patch) | |
| tree | 3d54a182709bc45c16e276cc33e36f01cbe7f4ee /target/arm/translate.h | |
| parent | 797ed66d29909e9564b146a4a181005fc8096c69 (diff) | |
| download | qemu-9c489ea6bed134fecfd556b439c68bba48fbe102.tar.gz | |
tcg: Pass generic CPUState to gen_intermediate_code()
Needed to implement a target-agnostic gen_intermediate_code()
in the future.
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Alex Benneé <alex.benee@linaro.org>
Reviewed-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu>
Message-Id: <150002025498.22386.18051908483085660588.stgit@frigg.lan>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target/arm/translate.h')
| -rw-r--r-- | target/arm/translate.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target/arm/translate.h b/target/arm/translate.h index 12fd79ba8e..2fe144baa9 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -149,7 +149,7 @@ static void disas_set_insn_syndrome(DisasContext *s, uint32_t syn) #ifdef TARGET_AARCH64 void a64_translate_init(void); -void gen_intermediate_code_a64(ARMCPU *cpu, TranslationBlock *tb); +void gen_intermediate_code_a64(CPUState *cpu, TranslationBlock *tb); void gen_a64_set_pc_im(uint64_t val); void aarch64_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, int flags); @@ -158,7 +158,7 @@ static inline void a64_translate_init(void) { } -static inline void gen_intermediate_code_a64(ARMCPU *cpu, TranslationBlock *tb) +static inline void gen_intermediate_code_a64(CPUState *cpu, TranslationBlock *tb) { } |