diff options
| author | James Hogan <james.hogan@imgtec.com> | 2017-07-18 12:55:56 +0100 |
|---|---|---|
| committer | Yongbok Kim <yongbok.kim@imgtec.com> | 2017-07-20 22:42:26 +0100 |
| commit | cec56a733dd2c3fa81dbedbecf03922258747f7d (patch) | |
| tree | c8cac93783b4fd91c05c7ef2ef58b958961be694 /target/mips/machine.c | |
| parent | 42c86612d507c2a8789f2b8d920a244693c4ef7b (diff) | |
| download | qemu-cec56a733dd2c3fa81dbedbecf03922258747f7d.tar.gz | |
target/mips: Add segmentation control registers
The optional segmentation control registers CP0_SegCtl0, CP0_SegCtl1 &
CP0_SegCtl2 control the behaviour and required privilege of the legacy
virtual memory segments.
Add them to the CP0 interface so they can be read and written when
CP0_Config3.SC=1, and initialise them to describe the standard legacy
layout so they can be used in future patches regardless of whether they
are exposed to the guest.
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Yongbok Kim <yongbok.kim@imgtec.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
Diffstat (limited to 'target/mips/machine.c')
| -rw-r--r-- | target/mips/machine.c | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/target/mips/machine.c b/target/mips/machine.c index 91e31a7c2f..898825de3b 100644 --- a/target/mips/machine.c +++ b/target/mips/machine.c @@ -211,8 +211,8 @@ const VMStateDescription vmstate_tlb = { const VMStateDescription vmstate_mips_cpu = { .name = "cpu", - .version_id = 9, - .minimum_version_id = 9, + .version_id = 10, + .minimum_version_id = 10, .post_load = cpu_post_load, .fields = (VMStateField[]) { /* Active TC */ @@ -252,6 +252,9 @@ const VMStateDescription vmstate_mips_cpu = { VMSTATE_UINTTL(env.CP0_Context, MIPSCPU), VMSTATE_INT32(env.CP0_PageMask, MIPSCPU), VMSTATE_INT32(env.CP0_PageGrain, MIPSCPU), + VMSTATE_UINTTL(env.CP0_SegCtl0, MIPSCPU), + VMSTATE_UINTTL(env.CP0_SegCtl1, MIPSCPU), + VMSTATE_UINTTL(env.CP0_SegCtl2, MIPSCPU), VMSTATE_INT32(env.CP0_Wired, MIPSCPU), VMSTATE_INT32(env.CP0_SRSConf0, MIPSCPU), VMSTATE_INT32(env.CP0_SRSConf1, MIPSCPU), |